Semiconductor memory device

Abstract

With a semiconductor memory device according to the invention, it is possible to perform level shift of a word driver by a change in voltage at a line for a word driver P-channel control signal connected to a P-channel transistor, without a change in size of the P-channel transistor and that of an N-channel transistor, even at a low voltage of output from a row decoder. Thus, it is possible to maintain a small size ratio between the N-channel transistor and the P-channel transistor.

Description

technical field [0001] The present invention relates to a semiconductor storage device in which a memory cell array composed of a plurality of memory cells is provided, and the memory cell array is selected and driven by a word line selection circuit and a word line drive circuit to store data. Background technique [0002] Conventionally, as a semiconductor memory device, a dynamic random access memory (hereinafter, abbreviated as DRAM) in which a memory cell array composed of a plurality of memory cells is provided and data is stored in the memory cell array has been widely used. [0003] In such a DRAM, a plurality of word lines are connected to a memory cell array, and each word line of these word lines is respectively connected to a plurality of memory selection transistors constituting a word line selection circuit and a word driver constituting a word line drive circuit. driver. [0004] In the above-mentioned DRAM, if a certain word driver is selected, the word line...

AI Technical Summary

Problems solved by technology

[0017] As described above, it is difficult to achieve both high-speed operation and low-power-supply-voltage operation in the level shifter of conventional semiconductor memory devices.

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