Semiconductor package structure and its making method
A manufacturing method and packaging structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of increasing package size, reducing the performance of organic substrates, and large stress, so as to increase reliability , reduce stress and improve electronic performance
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[0034] The implementation mode of the preferred embodiment of the present invention will be described in detail below, the present invention provides many suitable inventive concepts, and these inventive concepts can be implemented under several different conditions, and the embodiment described below is only as the example of implementing the present invention , but it is not intended to limit the present invention.
[0035] An embodiment of the present invention provides a method for packaging a semiconductor chip using an ultra-thin packaging substrate. The intermediate process stages of the embodiments of the present invention will be described below, and the changes of the embodiments will also be described below. In the embodiments, similar elements will be marked with similar symbols.
[0036]The stress in the packaging system is related to various factors, such as the material of the underfill or the thickness of the semiconductor chip. Please refer to FIG. 1 , which ...
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