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Semiconductor package structure and its making method

A manufacturing method and packaging structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of increasing package size, reducing the performance of organic substrates, and large stress, so as to increase reliability , reduce stress and improve electronic performance

Active Publication Date: 2007-10-24
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

The assembly of multiple chips (multi chips) on the same substrate can improve electronic performance while shortening the connection path between components. However, the larger package size also produces greater stress, which in turn affects the packaging process and Packaging problems caused by reliability testing
[0006] At present, advanced substrate materials such as organic substrates are commonly used in the packaging industry, which have the advantage of low cost. However, due to routing limitations, the performance of organic substrates is reduced, making it impossible to increase the package size to improve electronic performance. achieve

Method used

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  • Semiconductor package structure and its making method
  • Semiconductor package structure and its making method
  • Semiconductor package structure and its making method

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Embodiment Construction

[0034] The implementation mode of the preferred embodiment of the present invention will be described in detail below, the present invention provides many suitable inventive concepts, and these inventive concepts can be implemented under several different conditions, and the embodiment described below is only as the example of implementing the present invention , but it is not intended to limit the present invention.

[0035] An embodiment of the present invention provides a method for packaging a semiconductor chip using an ultra-thin packaging substrate. The intermediate process stages of the embodiments of the present invention will be described below, and the changes of the embodiments will also be described below. In the embodiments, similar elements will be marked with similar symbols.

[0036]The stress in the packaging system is related to various factors, such as the material of the underfill or the thickness of the semiconductor chip. Please refer to FIG. 1 , which ...

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Abstract

A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an interconnect structure overlying the package substrate, attaching at least one chip to a first surface of the package substrate, thinning the package substrate from a second surface opposite the first surface wherein the semiconductor material is substantially removed, and attaching ball grid array (BGA) balls to deep vias exposed on the second surface of the package substrate after thinning the package substrate.

Description

technical field [0001] The present invention relates to an integrated circuit package, and in particular to a material and method capable of reducing stress in an integrated circuit package structure. Background technique [0002] At present, the manufacture of integrated circuits generally includes multiple process steps. First, the integrated circuits are formed on a wafer. The wafer includes a plurality of repeated semiconductor chips (chips), and each chip includes an integrated circuit. Next, the semiconductor chip is cut from the wafer and subjected to a chip packaging process. Die packaging serves two purposes: to protect the fragile semiconductor die and to connect the internal integrated circuits to external pins. [0003] In the known packaging process, the semiconductor chip is fixed on the organic substrate by flip-chip bonding or wire bonding. In terms of flip-chip technology, the gap between the chip and the packaging substrate is Fill in the underfill (under...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L21/60H01L23/488H01L23/498
CPCH01L2924/01074H01L24/48H01L23/055H01L2224/97H01L2224/73253H01L2924/15184H01L2924/01047H01L2224/48227H01L2924/15311H01L2924/014H01L24/97H01L21/6835H01L2924/01322H01L2924/01029H01L2224/16H01L2224/73204H01L23/36H01L21/563H01L2924/01013H01L2924/01082H01L2924/01033H01L2224/32225H01L2924/01015H01L23/49816H01L23/3121H01L2924/10253H01L2224/73265H01L2924/157H01L2924/01327H01L2924/01032H01L2924/01006H01L2224/32145H01L2224/73203H01L2924/01019H01L2224/16225H01L2924/14H01L2224/48145H01L2924/12044H01L24/73H01L2224/451H01L2924/00014H01L2924/181H01L2924/351H01L2224/81H01L2224/83H01L2224/85H01L2924/00H01L2924/00012H01L2224/45099H01L2224/05599
Inventor 卢思维赵智杰郭祖宽邹觉伦张国钦
Owner TAIWAN SEMICON MFG CO LTD
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