Chip overlap structure and wafer structure for manufacturing the chip stack structure

Abstract

The disclosed chip stack structure comprises: two chips, a protective layer on the active face of first chip to clad the second chip, and first conductive pole inserted in the protective layer to make one end connect with first joint point and another out of the protective layer, wherein the second chip is stacked on the first one, the back face of the second chip is toward the active face of the first chip. The second chip comprises a first joint point on its active face. The product is thin.

Description

【Technical field】 [0001] The present invention relates to a chip package structure and a wafer structure for manufacturing the chip package structure, in particular to a chip stack structure (stacked structure of chips), and A wafer structure for manufacturing the chip stack structure. 【Background technique】 [0002] In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. As far as product appearance is concerned, the design of electronic products is moving towards the trend of light, thin, short and small. In order to achieve the above purpose, many companies incorporate the concept of systemization when designing circuits, so that a single chip can have multiple functions, so as to save the number of chips configured in electronic products. In addition, as far as electronic packaging technology is concerned, in order to meet the trend of light, thin, short and small design, packaging design concepts such as m...

AI Technical Summary

Problems solved by technology

[0005] It is worth noting that since the package carrier 210 and the chip 220 have a certain thickness, and the bumps 230 and the solder balls 250 also have a certain height, the chip packages 200a and 200b also have a certain thickness and are difficult to reduce

Therefore, when the conventional multi-chip packages (200a, 200b...) are stacked to form the chip package stack structure 100, the thickness of the chip package stack structure 100 will often increase rapidly, thus Does not meet design needs

[0006] Therefore, under the limitation of a fixed volume or thickness, it is difficult to further improve the packing density of the chip package stack structure 100.

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