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PLL device and current compensation method

A phase-locked loop and current compensation technology, which is applied in the direction of electrical components, automatic power control, etc.

Active Publication Date: 2011-08-31
XUESHAN TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the semiconductor process, capacitors C1 and C2 are implemented in the form of transistors, and the thin gate oxide layer of transistors manufactured by 0.18μm (micrometer), 0.13μm or other more advanced processes may cause leakage current

Method used

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  • PLL device and current compensation method
  • PLL device and current compensation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0030] image 3 It is a schematic diagram showing the architecture of a phase-locked loop (PLL) device with a current compensation circuit according to an embodiment of the present invention. The PFD unit 31 receives the reference clock signal REF_CLK and the feedback clock signal FBK_CLK and measures the phase difference and frequency difference between them to output phase difference signals UP and DN. The charge pump circuit 32 receives the phase difference signals UP and DN and converts them into currents to charge the loop filter 33 . The loop filter 33 includes a capacitor C31 coupled to the ground and the node N1, a resistor R1 coupled to the node N1, and a capacitor C32 coupled to the ground. In this embodiment, capacitors C31 and C32 are realized by transistors, and the current I 31 with I 32 represent the leakage currents of capacitors C31 and C32, respectively. The voltage controlled oscillator (voltage controlled oscillator, VCO) 34 is based on the control volt...

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PUM

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Abstract

The invention provides a PLL device comprising a PFD unit, a charging pump circuit, a loop filter, an oscillator, a feedback divider and a current compensation circuit. The PFD unit measures a phase and a frequency difference between a reference clock signal and a feedback clock signal of the PLL device to output a difference signal UP and a difference signal DN. The charging pump circuit receives and transfers the difference signals UP and DN into a current. The loop filter receives and transfers the current into a voltage. The oscillator receives the voltage and outputs an output signal. The feedback divider having a parameter N receives the output signal to generate the feedback clock signal according to the parameter N, wherein a frequency of the feedback clock signal is N times a frequency of the output signal. When the reference clock signal leads the feedback clock signal, the current compensation circuit outputs a compensation current to the loop filter.

Description

technical field [0001] The present invention relates to a Phase Lock Loop (PLL) device, and more particularly to a PLL device with a current compensation circuit. Background technique [0002] The PLL device is a main component used in frequency generators, wireless receivers, and communication devices. see figure 1 . figure 1 is a schematic diagram showing the architecture of a conventional PLL device. The phase and frequency detection (PFD) unit 11 receives the reference clock signal REF_CK and the feedback clock signal FBK_CK and measures the phase difference and frequency difference between them to output phase difference signals UP and DN. A charge pump circuit 12 receives the phase difference signals UP and DN and converts the phase difference signals UP and DN into currents to charge the loop filter 13 . exist figure 1 A circuit diagram of a conventional loop filter 13 is provided in . The loop filter 13 limits the capacitor voltage V by receiving the current fr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/085
CPCH03L7/095H03L7/087H03L7/18H03L7/0891
Inventor 黄志坚陈建铭
Owner XUESHAN TECH INC