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Method for forming shallow groove isolation structure in deep groove and its application

An isolation structure, deep trench technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as difficulty in controlling the depth of the buried conductive strip 26

Inactive Publication Date: 2008-02-27
PROMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the known process of deep trench capacitors, there are usually many problems, including difficult to control the depth of the buried conductive strip 26 in the deep trench structure 22, easy to form voids in the shallow trench isolation region 27, And, from the perspective of looking down on the wafer, it is easy for the active region 30 to form a striated outline, etc.
The above-mentioned problems all have varying degrees of impact on the normal performance of DRAM components

Method used

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  • Method for forming shallow groove isolation structure in deep groove and its application
  • Method for forming shallow groove isolation structure in deep groove and its application
  • Method for forming shallow groove isolation structure in deep groove and its application

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Embodiment Construction

[0028] The present inventor has studied the conventional deep trench capacitor manufacturing process and found that the aforementioned problems are caused by the fact that the insulating layer on the substrate has an uneven surface during the manufacturing process, and the uneven surface is due to the non-flat surface in the manufacturing process. Expected from improper etching. The uneven pad insulating layer surface will make it impossible to provide a fixed height horizontal reference plane when measuring the depth of the buried conductive strip in the deep trench capacitor structure during the manufacturing process, thus causing the buried conductive strip to be deep. Depth control in trench capacitor structures is not easy.

[0029] The reasons for the formation of the aforementioned uneven surface of the pad insulating layer will be described below with reference to the accompanying drawings. First, please refer to FIG. 3A , which shows a pad insulating layer 12 formed ...

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Abstract

The present invention is a method of forming shallow-trench isolated structure in deep trench and its application. The deep trench which is located in substrate contains upper electrode and first insulating layer above the upper electrode, and the substrate has a insulating pad layer on its surface. The method includes: a hard mask layer is formed on the first insulating layer; first part of the hard mask layer is doped; the un-doped part of the first insulating layer is removed to expose part of the upper electrode; conducting layer is formed above the exposed upper electrode, and superior margin of the conducting layer keeps a certain depth from the surface of the insulating pad layer.

Description

technical field [0001] The present invention relates to a method for forming a shallow trench isolation structure in a deep trench and the application of the method, in particular to applying the method to the manufacture of dynamic random access memory elements, especially the dynamic random access memory elements with deep trench capacitance manufacture. Background technique [0002] With the development of deep sub-micron or even nanometer process technology for semiconductor components, the requirements for miniaturization and high integration of components are increasing. For a DRAM (Dynamic Random Access Memory; DRAM) structure, it must meet the requirements of smaller size but increased memory capacity. Therefore, in the past, the design and manufacturing method of capacitors in DRAM must be changed in order to conform to the evolution of the trend. [0003] According to the structure of the included capacitors, the current common DRAM can be divided into two types,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8242H01L21/762H10B12/00
Inventor 郭文硕钟朝喜李永尧李惠民
Owner PROMOS TECH INC