Method for manufacturing semi-conductor shallow ridges and deep groove
A semiconductor and deep groove technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increasing process complexity, high engraving accuracy, and large occupation, so as to reduce production costs and simplify process steps , easy-to-achieve effects
Inactive Publication Date: 2008-03-12
SHANGHAI HUA HONG NEC ELECTRONICS
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The LOCOS (Local Oxidation Isolation of Silicon) process is used for the upper part of the traditional deep trench isolation, which occupies a large area; there are also some methods that make shallow trenches first, and then deep trenches at the positions of large shallow trenches. The resulting structure is shown in Figure 1. As shown, the structure first makes shallow grooves, and deep grooves 11 are made at the position of the large shallow grooves. It can be seen from the figure that the large shallow grooves at the deep groove 11 will occupy a large area, and this manufacturing method also requires a relatively large area. High overlay accuracy (alignment); and the shallow groove is made first, and then the deep groove is made, and the isolation manufacturing needs to be completed separately, which also increases the complexity of the process
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[0018] The method for making semiconductor shallow grooves and deep grooves in the present invention comprises the following steps in turn:
[0019] (1) Deposit a hard mask on the silicon substrate 1, the hard mask includes a layer of silicon oxide 2 and a layer of silicon nitride 3, as shown in Figure 2;
[0020] (2) Coat photoresist 4, photolithography forms deep groove etch pattern, as shown in Figure 3; Etch deep groove, remove photoresist, thermal oxidation, form sidewall oxide layer 5 at deep groove sidewall and bottom ,As shown in Figure 4;
[0021] (3) Fill the deep groove with undoped polysilicon 6, etch back, and remove the polysilicon in other regions, as shown in Figure 5;
[0022] (4) Photoresist 7 is coated, photoresist 7 covers deep groove, and photolithography forms shallow groove etch pattern, as shown in Figure 6;
[0023] (5) etch the shallow groove 8, as shown in Figure 7, remove photoresist, thermal oxidation, form sidewall oxide layer 9 on the upper sid...
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The invention discloses a manufacturing method for deep groove and shallow groove, which requires the deep groove making first and then the shallow groove making when padding the stuffing into the deep groove to more than half and simultaneously fully packing the deep groove and shallow groove high-integrity with oxide. Thus the top packing of the deep groove can be accomplished by STI process to reduce the isolation area of deep groove and packing both deep and shallow grooves with lower standard of photoetching and alignment precision, which simplify the technological process and the complexity.
Description
technical field [0001] The invention relates to a method for manufacturing a semiconductor groove, in particular to a method for manufacturing a semiconductor shallow groove and a deep groove. Background technique [0002] The combination of deep trench isolation and shallow trench isolation has been paid more and more attention in Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) devices. Deep trenches can suppress the latch-up effect (1atch up) and isolate bipolar (bipolar transistor) devices, while shallow trenches are mainly used to isolate CMOS devices. Therefore, for BiCMOS devices, both deep trench isolation and shallow trench isolation are used. . The LOCOS (Local Oxidation Isolation of Silicon) process is used for the upper part of the traditional deep trench isolation, which occupies a large area; there are also some methods that make shallow trenches first, and then deep trenches at the positions of large shallow trenches. The resulting structure is shown ...
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IPC IPC(8): H01L21/762
Inventor 李永海周正良
Owner SHANGHAI HUA HONG NEC ELECTRONICS