Burr testing apparatus

Abstract

The invention discloses a burr detection device that consists of a double bounce inspection circuit and a reset control circuit; if the detected input signals have rising edge or descending edge, the double bounce edge inspection circuit outputs signals that have double bounce edge. The reset control circuit outputs a reset narrow pulse within each sample circle under the action of the clock edge so as to reset each sample circle of the double bounce edge inspection circuit and clean the locked signals that has rising and falling edge. Thus, the double bounce edge inspection circuit has rising edge and falling edge signals only in the sample circle to output signals that has double bounce that is the burr signals. The invention has direct indication for the burr inspection needless of comparing two types of sampling data; at the same time, the level status of the detected input signals does not need time to be inspected. Compared with prior art, the invention is needless of data comparing under the situation of delay, sampling or locking, the circuit is simple and is easy to be realized.

Description

technical field [0001] The invention belongs to the field of digital system testing and analysis, and in particular relates to a burr detection device. Background technique [0002] A logic analyzer is an instrument for analyzing digital system hardware and software, and is one of the most important data domain test instruments. Glitch detection is an important capability of a logic analyzer. A glitch is a narrow pulse whose width is smaller than the specified requirement. In logic analysis, it is considered that a narrow pulse that passes the threshold twice within one sampling clock cycle is a glitch. There are four types of common glitches: positive glitches that appear on the low level of the signal, negative glitches that appear on the high level of the signal, continuous glitches, and glitches that appear on the signal transition edge. Glitch is a false signal caused by interference, transmission delay and competition risk, etc., which will cause the system to work a...

AI Technical Summary

Problems solved by technology

[0012] Due to the time delay between D flip-flop D1 and D flip-flop D2 in Figure 1 and the feedback signal, some circuits must use separate devices, making the circuit structure complex, and as shown in Figure 3, the change of the output databack of D flip-flop D2 There is a certain time delay relative to the input signal, that is, it takes a certain time to confirm the level state of the input signal. If the signal has a glitch at this time, it will not be detected. Therefore, it cannot detect the glitch that appears on the jump edge

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