Insulation layer and semiconductor conducting layer aligning error electrical testing structure in micro-electro-mechanical system

A micro-electromechanical system and alignment error technology, which is applied in semiconductor/solid-state device testing/measurement, microstructure technology, electric solid-state devices, etc., can solve problems such as alignment error extraction, achieve consistent measurement methods, simple test equipment, The effect of simple test methods

CN101144701AInactive Publication Date: 2008-03-19SOUTHEAST UNIV
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2008-03-19
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention relates to an electricity test structure of an alignment error of an isolation layer graph and a semiconductor conducting layer graph in a microcomputer electrical system part process. The test structure of the alignment error is designed with a metallic layer as a base layer, a semiconductor layer in the structure is a semiconductor that two blocks are separated, the material is same and the graph is different, one block is a ladder type, the other block is a rectangular, the both blocks are parallel; a metallic layer that is touched with the semiconductor layer and forms a connection is two metal strips that are parallel and have an interval, wherein, the upper and lower bottoms of the ladder type and two long edges of the rectangular are vertically covered with one strip, the obtuse angle part of the ladder type and the two long edges of the rectangular are covered with the other strip and truncated in the isolation region between two semiconductors, the part of the metal strip is respectively corresponding to the isolation layer under the semiconductor layer, a strip pin hole is established accordingly, the size of the pin hole is less than the metal strip of a corresponding part and can cover the same part of the ladder type semiconductor and the rectangular semiconductor like the metal strip, a resistance provided with a connecting line is formed in common by two metallic strips and the semiconductor between the two metallic strips, when a relative offset is existent between the isolation layer graph and the semiconductor conducting layer graph, the R2 change is tested, and the alignment error of the isolation layer graph and semiconductor conducting layer graph are obtained.
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Description

technical field

[0001] The invention relates to a micro-electro-mechanical system (MEMS) device processing technology, in particular to an electrical test structure for the alignment error of an insulating layer and a semiconductor conductive layer pattern in the processing of a micro-electro-mechanical system device, belonging to the fields of electricity and semiconductors. Background technique

[0002] There are many layers of materials in microelectromechanical systems (MEMS) device processing, including both conductive layer materials and insulating layer materials. There is an overlay alignment problem among these material layer patterns, that is, there is a requirement that subsequent material layer patterns be aligned with previous material layer patterns.

[0003] The traditional overlay alignment is to adopt the method of mutual nesting of large and small graphics, that is, to design the same graphics of different sizes on different layers with registration require...

Examples

Embodiment Construction

[0014] Fig. 1 shows the test structure graph of the pattern error of the insulation layer pattern aligned with the semiconductor conductive layer pattern, and the cross-sectional structure of the structure is also shown in the figure. In the test structure, 102 is a trapezoid and 104 is a rectangle. The material of these two patterns is a semiconductor material layer, which can be polysilicon 1 or polysilicon 2. They all have conductivity due to doping, of course, they must There is resistance. 103, 106, 108 are lead wire holes opened on the insulating layer 109, 101, 105, 107 are strip-shaped metal layers, covered on the holes of the insulating layer, and its size is greater than the size of the hole, so as to ensure the connection between the metal pattern and the insulating layer. The hole can still be completely covered when the layer pattern is offset. 110 is an insulating material, usually silicon nitride. 111 is a silicon substrate. The semiconductor conductive layer...