Insulation layer and semiconductor conducting layer aligning error electrical testing structure in micro-electro-mechanical system

Abstract

The invention relates to an electricity test structure of an alignment error of an isolation layer graph and a semiconductor conducting layer graph in a microcomputer electrical system part process. The test structure of the alignment error is designed with a metallic layer as a base layer, a semiconductor layer in the structure is a semiconductor that two blocks are separated, the material is same and the graph is different, one block is a ladder type, the other block is a rectangular, the both blocks are parallel; a metallic layer that is touched with the semiconductor layer and forms a connection is two metal strips that are parallel and have an interval, wherein, the upper and lower bottoms of the ladder type and two long edges of the rectangular are vertically covered with one strip, the obtuse angle part of the ladder type and the two long edges of the rectangular are covered with the other strip and truncated in the isolation region between two semiconductors, the part of the metal strip is respectively corresponding to the isolation layer under the semiconductor layer, a strip pin hole is established accordingly, the size of the pin hole is less than the metal strip of a corresponding part and can cover the same part of the ladder type semiconductor and the rectangular semiconductor like the metal strip, a resistance provided with a connecting line is formed in common by two metallic strips and the semiconductor between the two metallic strips, when a relative offset is existent between the isolation layer graph and the semiconductor conducting layer graph, the R2 change is tested, and the alignment error of the isolation layer graph and semiconductor conducting layer graph are obtained.

Description

technical field [0001] The invention relates to a micro-electro-mechanical system (MEMS) device processing technology, in particular to an electrical test structure for the alignment error of an insulating layer and a semiconductor conductive layer pattern in the processing of a micro-electro-mechanical system device, belonging to the fields of electricity and semiconductors. Background technique [0002] There are many layers of materials in microelectromechanical systems (MEMS) device processing, including both conductive layer materials and insulating layer materials. There is an overlay alignment problem among these material layer patterns, that is, there is a requirement that subsequent material layer patterns be aligned with previous material layer patterns. [0003] The traditional overlay alignment is to adopt the method of mutual nesting of large and small graphics, that is, to design the same graphics of different sizes on different layers with registration require...

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Problems solved by technology

At present, electrical parameters, geometric dimension parameters and errors can be extract

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