On-spot programmable gate array data cache management method

Abstract

The invention discloses a managing method for gate array data cache which can be programmed, when data is written, firstly, a writing operating module writes slicing data into a data memory, and records the length of the slicing data and gains the starting address in the data memory of the slicing data, and secondly, the writing operating module writes the length of the slicing data and the staring address in the data memory into the a storing controller. When data is read, firstly, a reading operating module reads the length of the slicing data which is gained by the storing controller and the staring address in the data memory, and secondly, the reading operating module reads the slicing data after giving the reading address of the data memory according to the staring address. The position of each massage slicing in the data memory is led to gain explicit mark by the technical proposal of the invention.

Description

technical field [0001] The invention relates to a data buffer management method, in particular to a FPGA (Field Programmable Gate Array, Field Programmable Gate Array) data buffer management method. Background technique [0002] When the FPGA receives the data to be processed, it writes the data into the data FIFO (FirstInput FirstOutput, first-in-first-out queue), that is, the data memory, and writes the control information into the control FIFO, that is, the storage controller; when the control FIFO is not empty , indicating that there is data. The downstream module reads the control FIFO0 to get the control information, and then reads the corresponding data from the data FIFO for processing. [0003] A conventional FIFO implementation includes a FIFO controller and a dual-port RAM (random-access memory, random-access memory). One port of the dual-port RAM is used as a write port, while the other port is used as a read port, and the read and write ports operate independen...

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Problems solved by technology

However, the read-write address of its dual-port RAM is generated by the FIFO controller, and the external module that initiates the write operation or read operation cannot know the current read-write address. Once an operation error occurs in the write module and the read module, it will cause the entire The internal and subsequent data in the RAM are chaotic and cannot be recovered; moreover, in this patent, the messages of different channels are cached by channel, requiring each channel to have a set of FIFO control information, such as read and write address pointers, empty and full status indication, Number of counters, etc., when the number of channels is large, it will lead to inconvenient management and waste of logic resources; moreover, a depth constant needs to be set in this patent, and multiple channels need multiple different depth constants

[0004] The U.S. Patent No. "US5664116" describes a method of message buffering, that is, each channel is allocated a separate FIFO to buffer data, but each The position of each message fragment in the data FIFO is not clearly identified. Once an error occurs in one of the read and write operations, the data in the entire buffer area will be read out of order, resulting in an irrecoverable error.

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