A device and method for low-density checksum LDPC parallel coding

A low-density check code and LDPC code technology, which is applied in the field of low-density check code LDPC parallel encoding devices, can solve problems such as constraints on the implementation of LDPC code encoding, no implementation plan, and difficulty in applying high-speed data transmission systems, etc., to achieve Improve coding efficiency, avoid multiplication operations, and enhance scalability

Inactive Publication Date: 2008-06-04
HUAWEI TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the serial coding scheme, that is, method 1, although the structure is relatively simple, the coding efficiency is relatively low, and it is difficult to apply to high-speed data transmission systems; for the full parallel coding scheme, that is, method 2, although the coding speed can be effectively improved, the hardware The complexity is high, the storage space is large, and it is difficult to implement; the parallel encoding scheme of multiplying small matrices, that is, method 3, can effectively improve the encoding speed, and the complexity of hardware implementation is relatively lo

Method used

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  • A device and method for low-density checksum LDPC parallel coding
  • A device and method for low-density checksum LDPC parallel coding
  • A device and method for low-density checksum LDPC parallel coding

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specific Embodiment

[0148] The following takes the 1 / 2 code rate LDPC code in IEEE P802.16e as an example to illustrate the specific implementation process of the encoding. Table 1 shows the base matrix H corresponding to the parity check matrix of the LDPC code bm , where n b =24, m b =12, z=96, code length n=2304, 1~12 columns of the matrix correspond to information bits, 13~24 columns correspond to parity bits, -1 corresponds to z×z zero matrix, and others correspond to z×z unit matrix to the right number of cycles.

[0149] Table 1 The base matrix of the 1 / 2 code rate LDPC parity check matrix

[0150] 1

2

3

4

-5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

1

-1

94

7

3

-1

-1

-1

-1

-1

55

83

-...

Embodiment 1

[0154] Embodiment 1: According to the technical solution, for the first precoder design process, H bm Remove the last line, and then remove the following m b -1 column, that is, remove the twelfth row in Table 1 and then remove the following 11 columns to form H″ b1 is 11×13, namely H′ given in formula (11b) bm1 Remove the last line, H bm Remove the last 11 columns to form H″ b2 is 11×11, which is H′ given in formula (11b) bm2 Remove the last line, corresponding to the encoder such as Figure 9 As shown, there are four main devices including information storage unit, precoding unit, data allocation unit and convolutional coding unit, where the information storage unit contains 13 cyclic shift registers, and the precoding unit contains m b -1=11 modulo 2 adders, the convolutional coding unit contains m b -1 = 11 recursive convolutional encoders. For the design process of the second precoder, H bm Delete the first line in Table 1, and then delete the following m b -1 co...

Embodiment 2

[0175] Embodiment 2: For the second precoder design process, after the base matrix of the parity check matrix removes the first row in Table 1, then removes the following 11 columns to form H "' b1 is 11×13, that is, remove the first 13 columns of the base matrix of the LDPC code parity check matrix shown in Table 1 in the first row of Table 1 to form the sub-matrix H given in formula (11b) bm1 Remove the first row, and the remaining 11 columns constitute the sub-matrix H given in formula (11b) bm2 Remove the first line, corresponding to the encoder such as Figure 9 As shown, there are four main devices including information storage unit, precoding unit, data allocation unit and convolutional coding unit, where the information storage unit contains 13 cyclic shift registers, and the precoding unit contains m b -1=11 modulo 2 adders, the convolutional coding unit contains m b -1 = 11 recursive convolutional encoders. For the design process of the second precoder, the base m...

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Abstract

The invention relates to the communications field and provides parallel encoding device and a method for a low density parity-check code (LDPC). By adopting the practice of step-by-step encoding combined with the serial-parallel approach, a concatenated encoding scheme with linear complexity combining with pre-encoding and parallel convolution coding structures is provided thereby. The encoding device for realizing the encoding scheme mainly comprises an information storage unit, a pre-encoding unit and an encoding unit (comprising a data distribution unit and a convolution coding unit) as well as a v (0) verification bit generating unit. The encoding device of the invention adopts a circular shift register and a model 2 adder, which is easy to realize and avoid multiplication operation of vector and matrix. Complexity of the encoding device is reduced. The encoding device provided by the invention features good expansibility. A plurality of basic encoders are used for parallel encoding so that encoding efficiency can be improved by many times compared with the single basic encoding device. Therefore, when hardware complexity permits, parallel structures can be applied as much as possible, which greatly improves encoding efficiency.

Description

technical field [0001] The invention relates to the communication field, in particular to a device and method for parallel coding of low-density check code LDPC. Background technique [0002] Low-density parity check code LDPC was first proposed by Gallager in 1964 as a coding method with performance close to Shannon's limit. For a long time, due to the limitation of technological level, LDPC has not been paid attention to and promoted. , until 1996 when D.Mac Kay and R.Neal proved that the performance and cost of LDPC codes were superior to Turbo codes (a series of language software developed by BROLAND), LDPC codes entered people's field of vision again, setting off a wave of research. [0003] In the process of LDPC from theoretical research to practical development, the coding complexity and the resulting coding delay have become a key factor restricting the application of LDPC codes in high-speed data services. [0004] The LDPC code in IEEE 802.16e starts from the per...

Claims

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Application Information

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IPC IPC(8): H03M13/11H03M13/19H04L1/00
Inventor 李颖郭旭东李云岗王吉滨
Owner HUAWEI TECH CO LTD
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