Packaging conductive structure and its forming method

Abstract

The invention relates to an encapsulated conducting structure for a semiconductor substrate and the forming method thereof. The dielectric layer of the encapsulated conducting structure is locally covered with the metal layer of the semiconductor substrate, and defines an accommodation space with an elevating layer and a conducting layer inside, the conducting layer stretches to connect with a bump, and the elevating layer is connected with a dielectric layer , so that the deposition of the edge of the dielectric layer is stabilized, and thus improving the reliability of the encapsulated conducting structure.

Description

technical field [0001] The present invention relates to an encapsulation conductive structure for a semiconductor substrate; in particular, an encapsulation conductive structure with a redistribution layer. Background technique [0002] Today's electronic products usually have semiconductor chips to provide control or logic operation functions. Due to the continuous improvement of process technology, semiconductor chips are becoming smaller and smaller, and the package size is gradually shrinking. [0003] The traditional wire bonding (Wire Bonding) method of bonding semiconductor chips and other components of the electronic packaging technology has long been insufficient, and it has been replaced by the flip-chip bonding technology that uses bumps as chips and other components. In other words, a plurality of bumps are provided on the surface of the semiconductor chip, which are electrically connected to the internal structure and are used for bonding with other components, ...

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Problems solved by technology

[0006] However, in the process of forming the conductive layer 151, since the deposition of the conductive layer is unidirectional deposition, it is indeed difficult to form a conductive layer with a sufficient thickness on the sidewall of the dielectric layer 13, which may easily lead to the risk of disconnection.

like figure 1 As shown by the dotted line in , part of the conductive layer 151 near the sidewall of the dielectric layer 13 is relatively difficult to deposit. Once the process is not properly controlled, it is very likely to cause an open circuit and cause the semiconductor chip to fail.

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