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FPGA circuit fault detecting apparatus

A technology for detecting device and circuit faults, which is applied in the direction of redundant code error detection and response error generation, which can solve the problems of long fault detection delay, large system overhead, complex implementation, etc., and achieve power consumption optimization and system overhead Small and easy to achieve

Inactive Publication Date: 2008-10-01
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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Problems solved by technology

[0010] Aiming at the problems of large system overhead, long fault detection delay, and complex implementation of the current FPGA circuit soft fault detection method, the present invention provides a FPGA circuit fault detection device, which can not only quickly detect faults, but also has low system overhead and simple implementation

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Embodiment Construction

[0036] In order to make the purpose, technical solution and advantages of the present invention clearer, a FPGA circuit fault detection device of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0037] The invention proposes an efficient FPGA circuit fault detection device aiming at the problems of large system overhead, long fault detection delay, complex implementation and the like in the current FPGA circuit soft fault detection method.

[0038] Such as figure 1 As shown, the FPGA circuit fault detection device of the present invention includes an input signal encoder 10 , an output signal decoder 30 , at least one fault probe 22 , and a fault locator 24 .

[0039] The input signal encoder 10 is configured to perform time redundant encoding on ...

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Abstract

The present invention provides a FPGA circuit fault detection device, including an input signal encoder, an output signal encoder, at least one fault probe, and a fault positioner. The input signal encoder is used for processing time redundancy encode to the input signal; the output signal encoder is used for ensuring the detected FPGA circuit output correct result; the fault probe is used for processing time redundancy encode to the output of any point of the detected FPGA circuit, comparing the output result of the same input on the different time nodes, judging the detected FPGA circuit fault. The FPGA circuit fault detection device further includes a fault positioner, used for encoding the output result of the fault probe, locating the fault in a smaller local area. The device not only quickly detects the fault, but also having less system cost, simple realization.

Description

technical field [0001] The invention relates to the technical field of circuit fault tolerance, in particular to a field programmable gate array (FPGA) circuit fault detection device. Background technique [0002] Reliability is an important issue that must be considered in the computer design process. In order to improve the reliability of the system, various effective fault-tolerant technologies have been proposed, such as Triple Modular Redundancy (Triple Modular Redundancy, TMR) technology, Error Detection and Correction (Error Detection And Correction, EDAC) technology, parity check technology, sampling decision technology based on time redundancy, etc. These techniques can be mainly divided into three categories: area redundancy, time redundancy, and information redundancy. Information redundancy is mainly used in the fault tolerance of storage units. Most of the existing area redundancy and time redundancy fault tolerance technologies are aimed at traditional Applica...

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Application Information

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IPC IPC(8): G06F11/10
Inventor 邓珊珊章立生谢应科买鹏
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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