Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, to solve the problem in current semiconductor devices that a forming region of ISO is difficult to become narrow caused by lateral diffusion width extension of a P-type buried layer that forms ISO. In the semiconductor device of the invention, double layered EPIs (7) and (8) are formed on a P-substrate (6); ISOs (1), (2) and (3) are formed in the substrate (6) and the EPIs (7) and (8), which are divided into a plurality of islands. ISO (1) is formed by connecting L-ISO (9), M0ISO (10) and U-ISO (11). M-ISO (10) is disposed between L-ISO (9) and U-ISO (11), such that a lateral diffusion width (W1) of L-ISO (9) is reduced. With the structure, a forming region of ISO (1) becomes narrow.

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method. Background technique [0002] As an example of a conventional semiconductor device, the following structure of the NPN transistor 281 is known. As shown in FIG. 25 , an N-type epitaxial layer (hereinafter referred to as EPI) 283 is formed on a P-type semiconductor substrate 282 . In EPI 283 , P-type buried diffusion layers (hereinafter referred to as buried layers) 284 and 285 diffused upward and downward from the surface of substrate 282 , and P-type diffusion layers 286 and 287 diffused from the surface of EPI 283 are formed. Then, the EPI 283 is divided into a plurality of island regions (hereinafter referred to as islands) by isolation regions (hereinafter referred to as ISO) 288 and 289 formed by connecting the buried layers 284 and 285 and the diffusion layers 286 and 287 . In one island, for example, an NPN transistor 281 is formed. The NPN transistor 281 is...

AI Technical Summary

Problems solved by technology

In this case, the diffusion width W26 of the buried layer 307 and the diffusion width W27 of the diffusion layer 308 become wider, and there is a problem that it is difficult to reduce the device size of the NPN transistors 301 and 302.

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