Method for mapping video processor video data and memory space

A video processor and video data technology, which is applied in the field of digital video coding and decoding, can solve the problems that no solution is given, and the data access rate cannot be better improved, so as to achieve the effect of improving access bandwidth and ensuring normal operation

Inactive Publication Date: 2008-11-12
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This method can also be used for video decoders, but for video encoders, especially those using H.264 standard, MPEG4 standard and AVS standard, the search window involved in motion estimation often spans more data According to this method, the data access rate cannot be better improved, and there is no corresponding solution for selecting the appropriate storage space according to the video processing flow for the video image that needs to be stored for each frame.

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  • Method for mapping video processor video data and memory space
  • Method for mapping video processor video data and memory space
  • Method for mapping video processor video data and memory space

Examples

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Embodiment 1

[0049] Example 1: Encoder 7-frame storage scheme

[0050] The memory used is W986432DH 512K×4BANKS×32BITSDRAM of Winbond Company, the data bus bit width of this memory is 32 bits, and the number of pages Banknum is equal to 4; the resolution of the video image is 720×576, and the sampling format is 4:2:0; That is, the proportional relationship between the brightness pixel point Y and the number of two color difference pixel points Cb and Cr is: Y:Cb:Cr is equal to 4:1:1, P frame coding refers to 2 frames of images at most, between two consecutive P frames , or there are at most two B frames between the P frame and the I frame; the video processor requires a separate storage space for the original image and the reconstructed image, and the two do not overlap each other in the memory; the processed video sequence is a frame sequence.

[0051] From the bit width of the data bus of the memory, it can be obtained that: PPU is equal to 4, and the situation of PPU pixels occupying th...

Embodiment 2

[0061] Embodiment 2: Encoder 6-frame storage scheme

[0062] The memory used is W986432DH 512K×4BANKS×32BITSDRAM of Winbond Company, the data bus bit width of this memory is 32 bits, and the number of pages Banknum is equal to 4; the resolution of the video image is 720×576, and the sampling format is 4:2:0; That is, the proportional relationship between the brightness pixel point Y and the number of two color difference pixel points Cb and Cr is: Y:Cb:Cr is equal to 4:1:1, P frame coding refers to 2 frames of images at most, between two consecutive P frames , or there are at most two B frames between the P frame and the I frame; the video processor allows the original image and the reconstructed image to share the storage space, and they can overlap each other in the storage space; the processed video sequence is a field sequence.

[0063] From the bit width of the data bus of the memory, it can be obtained that: PPU is equal to 4, and the situation of PPU pixels occupying th...

Embodiment 3

[0072] Embodiment 3: Decoder 4 frame storage scheme

[0073] The memory used is the MT46V8M16 type DDR SDRAM of Micron Company, the data bus of the memory is 16 bits, and the page number Banknum is equal to 4; the resolution of the video image processed by the decoder is 720×576, and the sampling format is 4:2:0; P frame decoding refers to 2 frames of images at most, and supports B frame decoding function.

[0074] From the bit width of the data bus of the memory, it can be obtained that: PPU is equal to 2, and the situation of PPU pixels occupying the address bus is as follows Figure 12 shown.

[0075] According to the number of reference frames required for decoder P frame decoding, it can be obtained that the total number of video image frames to be stored is 4. For this reason, 4 groups of initial row addresses and initial column addresses are set in the memory: the first group of initial row addresses and initial column addresses are 0 and 0 respectively, represented b...

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PUM

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Abstract

The invention belongs to the technical field of digital video encoding and decoding, in particular relates to a mapping method of video data of a video processor and memory space of a memory which includes six steps. According to the mapping relation, the characters of concurrency, etc. of data access in different pages of the memory with a page structure are fully utilized. The luminance component and the chromaticity component of video images are divided, and mapped into the corresponding page address, row address and column address of the memory in the modes of luminance grouping and chromaticity grouping, so that the access bandwidth of the video processor to the video data is improved to a great extent. The memory, replacing and update processes inside the memory of the video images entering the memory are prescribed, thereby guaranteeing the normal operation of the video processor.

Description

technical field [0001] The invention belongs to the technical field of digital video encoding and decoding, and in particular relates to a mapping method between video data of a video processor and memory storage space. Background technique [0002] One of the main features of the video processor is the large amount of video data processed, which requires a high data bus bandwidth to meet the requirements of real-time video processing. Most of today's video codec processors use a hybrid video coding model, and the standards followed by the design include MPEG4, H.264, AVS, etc. These standards all use technologies such as spatial predictive coding, temporal predictive coding, and loop filtering. The biggest problem that these technologies bring to the design of video codec processors is that the codec processor needs to access a large amount of original image and reconstructed image data, which not only requires the video codec to be plugged with a large-capacity memory to s...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N11/04G06F12/02H04N19/156H04N19/182H04N19/42H04N19/433
Inventor 虞露王万丰张珂朱韵鹏
Owner ZHEJIANG UNIV
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