Soft and hard combined control stream checking method facing to embedded microprocessor

A microprocessor, a combination of software and hardware technology, applied in the direction of program control design, electrical digital data processing, error detection/correction, etc., can solve the problems of inconvenient hardware implementation and algorithm hardening implementation of the basic block division method

Inactive Publication Date: 2009-01-07
HARBIN ENG UNIV
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Problems solved by technology

However, because these methods are pure software methods, the basic block division method proposed in this paper

Method used

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  • Soft and hard combined control stream checking method facing to embedded microprocessor
  • Soft and hard combined control stream checking method facing to embedded microprocessor
  • Soft and hard combined control stream checking method facing to embedded microprocessor

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Embodiment Construction

[0072] The present invention is described in more detail below in conjunction with accompanying drawing example:

[0073] 1. Connect the system library assembly file and user assembly file: the specific operation is as follows:

[0074] The system file support is required when the user program calls the system library, such as Figure 8 In the traditional compilation process, the system library files have been generated by the assembler. The rel file is connected at the time of the linker. In order to perform a complete control flow inspection on the program, it is necessary to integrate the system library assembly file and the user library assembly file into a standard assembly file. The integration steps are as follows:

[0075] (1) Open the standard user assembly file and create an integrated assembly file;

[0076] (2) calling the lexical analysis module to carry out lexical analysis to the opened standard assembly file;

[0077] (3) read the morpheme from the assembly...

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Abstract

The present invention relates to an embedded microprocessor-oriented method for detecting a control flow combining software and hardware. The method comprising the steps of generating a standard assembly file from a running C language program, then linking a user library and a system library function included in the assembly file to form an integration assembly file by a lexical analysis method, implementing a basic block division to the integration assembly file through a signature generating program by the lexical analysis method, analyzing the control flow relation of the basic blocks, and signing for each basic block to form a new assembly file containing the control flow detection data. Then translating the assembly file into a target file by a modified assembler, and translating the target file into a binary mapping file by a linker, at last running the binary file in the embedded microprocessor with the control flow detection function. The invention achieves an average redundant code overhead of 12%, and as compared with hardware-based control flow detection methods, achieves higher simplicity in implementation, higher capability of control flow detection characterized by a non-detectable rate of only 1.5% on average, as well as lowered power consumption during system operation.

Description

(1) Technical field [0001] The invention relates to an embedded microprocessor-oriented software-hardware combination control flow detection method, which belongs to the technical field of trusted computing. (2) Background technology [0002] At present, the control flow detection technology is mainly used in the spaceborne computer system, and the reliability of the system can be improved by increasing the detection ability of the transient fault of the hardware. [0003] The traditional hardware-based control flow error detection methods are watchdog coprocessor and watchdog timer, both of which do not need to modify the program to be run, and do not need to add redundant detection code. A. Mahmood and E.J. McCluskey. Concurrent error detection using watchdog processors-asurvey. IEEE Transactions on Computers, 1988, 37(2): 160-174; H. Madeira, J. Camoes, and J.G. Silva. A watchdog processor for This is documented in concurrent error detection in multiple processor systems...

Claims

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Application Information

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IPC IPC(8): G06F9/45G06F11/00
CPCY02B60/181Y02D10/00
Inventor 吴艳霞顾国昌沈晶刘海波王克慧
Owner HARBIN ENG UNIV
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