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Random memory and electricity supplying method thereof

A technology of random access memory and power supply method, which is applied in static memory, instruments, etc., can solve the problems of shortened storage unit data retention time, reduced sensitivity of sensitive amplifiers, and reduced stability of random access memory, etc., to improve the initial voltage difference and increase stability , The effect of increasing the data retention time

Active Publication Date: 2009-01-07
GIGADEVICE SEMICON (BEIJING) INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In the process of realizing the present invention, the inventors have found that the reduction of the power supply voltage will at least cause: (1) the data retention time of the memory cell is shortened; (2) the initial voltage difference between the bit line and the complementary bit line is reduced; (3) The sensitivity of the sense amplifier is reduced
These will cause the stability of random access memory to decrease

Method used

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  • Random memory and electricity supplying method thereof
  • Random memory and electricity supplying method thereof
  • Random memory and electricity supplying method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] refer to Figure 4 The random access memory of this embodiment mainly includes: a logic control circuit 41, a memory array 42, a high-voltage charge pump 43, a voltage regulator 44, and the memory array 42 includes a memory cell array and a sense amplifier (not shown). Wherein, the logic control circuit 41 , the high-voltage charge pump 43 and the voltage regulator 44 are powered by the external power supply voltage Vdd. The high-voltage charge pump 43 converts Vdd to generate a voltage Vccs higher than Vdd, and uses the generated Vccs as the substrate bias voltage of the PMOS transistor of the memory cell array and the PMOS transistor of the sensitive amplifier; voltage regulator 44 Convert Vdd to generate a voltage Vcc higher than Vdd, and use the generated Vcc as the power supply voltage of the memory cell array and the sense amplifier.

[0031] It should be noted that how the high-voltage charge pump and the voltage regulator upgrade and convert the voltage is an e...

Embodiment 2

[0033] refer to Figure 5 , the random access memory of this embodiment mainly includes: a logic control circuit 51, a memory array 52, high-voltage charge pumps 53, 54, and the memory array 52 includes a memory cell array and a sense amplifier (not shown). Wherein, the logic control circuit 51 and the high-voltage charge pumps 53 and 54 are powered by the external power supply voltage Vdd. The high-voltage charge pump 53 converts Vdd to generate a voltage Vccs higher than Vdd, and uses the generated Vccs as the substrate bias voltage of the PMOS transistor of the memory cell array and the PMOS transistor of the sense amplifier; the high-voltage charge pump 54 Convert Vdd to generate a voltage Vcc higher than Vdd, and use the generated Vcc as the power supply voltage of the memory cell array and the sense amplifier.

[0034] In the second embodiment, there are two high-voltage charge pumps, which can also be realized by a separate high-voltage charge pump, that is, the extern...

Embodiment 3

[0037] refer to Figure 6, the random access memory of this embodiment mainly includes: a logic control circuit 61, a memory array 62, and a voltage generating module 63, and the memory array 62 includes a memory cell array and a sense amplifier (not shown). Wherein, the logic control circuit 61 and the voltage generation module 63 are powered by the external power supply voltage Vdd. The voltage generating module 63 converts Vdd to generate a voltage Vcc higher than Vdd, and uses the generated Vcc as a power supply voltage of the memory cell array and the sense amplifier. In this embodiment, NMOS transistors are used in the memory cell array and the sense amplifier, and the voltage provided for the substrate of the NMOS transistors does not need to undergo the above-mentioned boost conversion, but is directly provided with a low voltage by the logic control circuit 61 .

[0038] In the embodiment of the present invention, a voltage generation module is set in the random acc...

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Abstract

The invention provides a random access memory (RAM) and a power supply method thereof. The RAM comprises a voltage generation module which is used for boosting the external supply voltage, and the boosted voltage is provided for a memory array in the RAM. According to the RAM and the power supply method, the stability of the RAM under deep submicron technology and ultra-deep submicron technology can be effectively improved.

Description

technical field [0001] The invention relates to memory design, in particular to a random access memory and its power supply method. Background technique [0002] The random access memory can both write information to the specified unit and read information from the specified unit, refer to figure 1 , which is composed of a logic control circuit and a memory array, and the logic control circuit and the memory array are powered by the same external power supply voltage Vdd. The logic control circuit controls the reading and writing of random access memory and internal hidden refresh, including clock control circuit, address decoding circuit, input and output control circuit, etc.; memory array includes storage unit (cell) array and sense amplifier (SA), and the storage unit An array is an array of memory cells. [0003] figure 2 It is a schematic diagram of the internal structure of the memory array. refer to figure 2 , the memory array includes a plurality of memory ce...

Claims

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Application Information

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IPC IPC(8): G11C5/14
Inventor 朱一明刘奎伟
Owner GIGADEVICE SEMICON (BEIJING) INC
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