DSP high-efficient concurrency control method for JPEG2000 compression algorithm

Abstract

The invention belongs to the image compression field in the information technology, in particular to a DSP efficient concurrent control method in a JPEG2000 compression algorithm. The current data read from a first memory are processed under bit-plane scanning to produce results which are wrote into a second memory, meanwhile, the pervious group of data is shifted to an external cache from a third memory; and the data are read from the second memory and are processed under arithmetic coding to generate results which are wrote into the third memory, meanwhile, the next group of data is shifted into the first memory from the external cache. The invention makes the concurrent implementation of EBC algorithm operation and data shifting possible. The invention can execute the shifting process in the process of executing any cycle, and the shifting process is executed at the background without occupying the processing time of CPU, that is equivalent to the data shifting process without time spending, thereby realizing zero-time data shifting.

Description

Technical field [0001] The invention belongs to the field of image compression in information technology, and particularly relates to a DSP high-efficiency parallel control method in the JPEG2000 compression algorithm. Background technique [0002] As a new-generation still image compression standard, JPEG2000 can recover high-quality images while pursuing a high compression ratio. It has great application potential in the field of satellite-borne remote sensing image compression. However, the JPEG2000 compression algorithm has high complexity and slow coding speed, and its real-time implementation requires high hardware performance. The available devices are FPGA and DSP. However, the multiple if-then-else structure in the encoding algorithm is not conducive to FPGA implementation, so high-performance DSP is usually selected for implementation. [0003] The powerful processing capability of high-performance DSP is not only reflected in its high-speed core processing frequency, b...

AI Technical Summary

Problems solved by technology

DSP data memory read and write instructions support double-word read and write, that is, support 64-bit read and write, and have the potential to read and write four 16-bit wavelet data at a time, so the processing capacity of DSP has not been fully utilized

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