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Method for processing electric bottom layer oriented to integrate circuit digilogue mixing test adapter

A technology for testing adapters and integrated circuits, which is applied to the parts of electrical measuring instruments, the improvement of basic electrical components, and instruments, etc., to achieve the effect of high-speed signal transmission

Inactive Publication Date: 2009-02-11
BEIJING CHIPADVANCED
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the integrated circuit parallel test adapter still has certain deficiencies in overcoming the problem of noise interference generated by electricity and ground wires during the test process.

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] The invention is proposed based on the actual requirement of developing a high-speed multi-chip parallel test test adapter. In the process of developing the integrated circuit high-speed parallel test adapter, the inventor faced the problem that the test adapter has a high operating frequency and the noise interference generated by the power supply and the ground wire is relatively serious, and took the following technical measures:

[0016] 1. Introduce a decoupling capacitor between the power line and the ground line, and the decoupling capacitor should be as close as possible to the integrated circuit device itself.

[0017] Through the setting of the decoupling capacitor, the low-frequency part of the noise can be effectively filtered, and the adverse effect of the noise on the device can be eliminated as much as possible.

[0018] The selection of the specific size and model of the decoupling capacitor is well-known and competent to those skilled in the art, and wi...

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PUM

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Abstract

The invention discloses an electric strata processing method facing to a digital analogy mixed test adapter with an integrated circuit, which comprises the following steps of (1) introducing a decoupling capacitor between a power cord and a ground wire; (2) widening the width of the power cord and the ground wire in such a away that the ground wire is wider than the power cord; and (3) employing a large scale copper as the ground layer. By adopting the above method, the noise disturbance generated by the power cord and the ground wire is minimized, the quality of an integrated circuit product is fully ensured, and powerful technical support is provided for the further development of integrated circuit testing industry.

Description

technical field [0001] The invention relates to an implementation of integrated circuit high-speed parallel digital-analog hybrid test adapter, which can effectively solve the problem of noise interference generated by power supply and ground wire during the test process, and belongs to the technical field of integrated circuit testing. Background technique [0002] With the development of the integrated circuit industry, people generally use integrated circuit testers to detect the quality of integrated circuits. Since the 1980s, the integrated circuit tester has entered the fourth generation, and its measurement object is VLSI. The functional test rate of the tester has reached more than 500MHz, and the number of measurable pins is as high as 1024. [0003] At present, there are more and more applications of SoC (System on a Chip, System on a Chip) based on the mixture of digital and analog circuits, which has become a bright spot in the development of the integrated circu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R1/02G01R1/06G01R1/18G01R1/20G01R31/3167
Inventor 石志刚刘炜吉国凡张琳王慧孙博金兰赵智昊李尔孙杨
Owner BEIJING CHIPADVANCED
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