Clock generator based on phase-locked loop and clock generating method

Abstract

The invention discloses a clock generator based on a phase-locked loop, which comprises a crystal oscillator, a phase-locked loop circuit, a clock adjusting module and a doubling circuit output module, wherein the clock adjusting module is used for receiving a first multi-path clock signal output by the phase-locked loop circuit, respectively adjusts the frequency and the phase of each first multi-path clock signal according to the preset frequency and phase of a target clock signal, and outputs multiple second multi-path clock signals respectively corresponding to all of the first multi-pathclock signals; the doubling circuit output module is used for receiving and merging the second multi-path clock signals output by the clock adjusting module, and outputs the target clock signal with the preset frequency and phase. The invention also discloses a corresponding clock generating method. The clock generator based on a phase-locked loop and the clock generating method can conveniently and flexibly adjust the frequency and the phase of the output target clock signal, and greatly broaden the band width which can be realized.

Description

technical field [0001] The invention relates to the field of pulse generators, in particular to a phase-locked loop-based clock generator and a clock generation method. Background technique [0002] In an electronic system, the clock is equivalent to the heart, and the performance and stability of the clock directly determine the performance of the entire system. Currently, commonly used clock sources include a crystal oscillator (XO, also referred to as crystal oscillator) and a phase-locked loop (PLL) circuit. Among them, the crystal oscillator clock is usually only limited to work at one frequency, and the price of a more accurate crystal oscillator is relatively expensive. The phase-locked loop circuit is usually composed of a phase-frequency detector (PFD), a charge pump, a low-pass filter (LPF) and a voltage-controlled oscillator (VCO), because it can use a relatively cheap low-frequency crystal and has a wider frequency output range and higher design flexibility, an...

AI Technical Summary

Problems solved by technology

[0005] However, the clock signal output by this kind of clock generator based on the phase-locked loop can only be divided by two or four of the output frequency of the PLL circuit, and the output frequency cannot cover every point in the output frequency range. , and its maximum frequency will be limited by the oscillation frequency of the PLL circuit, and the bandwidth is narrow

Therefore, when the electronic system is relatively complex, it is still impossible to obtain all the required clock frequencies by using the above-mentioned existing clock generator based on the phase-locked loop only by using a single crystal oscillator. Different oscillators and phase-locked loops to obtain the required clock signals of different frequencies

[0006] In addition, the above-mentioned existing clock generator based on phase-locked loop also has the problems that the number of output phases is limited by the number of phases generated by the PLL, the adjustment step of the output frequency is too large, and the phase adjustment is limited by the accuracy of the digital multiplexer.

Images