Double-layer double-loop on chip network topology construction

Abstract

The present invention provides a double-layer double-ring on-chip network topology structure which comprises IP unit, an exchanging unit, a network adapter and a link unit. The exchanging unit realizes the mutual communication of each IP unit. A mechanism of combining time division multiplex and priority level is adopted. The space division multiplex of fair routing and bandwidth can be realized and simultaneously the congestion and deadlock can be effectively avoided. The link unit connects each unit according to a certain structure which adopts a double-layer double-ring structure. The first layer is a backbone looped network structure, and the second layer is a sub-network structure. The backbone looped network structure is a double-ring structure and is divided into two groups of looped networks, wherein one group of looped network is a main ring and the other group is a standby ring which is used for a fault tolerant mechanism of the on-chip network structure. Each group of ring comprises a control ring and a data ring. The ring network topology structure adopted by the invention has the advantages of simple structure, fixed hop number between the nodes, simple routing, easy realization of time division multiplex, space division multiplex and fault tolerance, etc.

Description

technical field [0001] The invention belongs to the field of on-chip interconnection network design, in particular to a double-layer double-ring type on-chip network topology structure with fair routing and space-division multiplexing of bandwidth. Background technique [0002] With the continuous development of semiconductor technology and the continuous improvement of System-on-Chip (SoC, System-on-Chip) technology, the number of IP cores included in the SoC continues to increase. The existing SoC technology based on the bus structure is facing huge challenges in terms of performance, power consumption, delay and reliability. Around 2001, some research institutes borrowed and absorbed the ideas of communication network and parallel computing, and proposed an IP core integration method for complex SoCs with communication as the core, that is, Network-on-Chip (NoC). The method of switching and routing replaces the traditional bus, and realizes the separation of the processi...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to solve various problems such as performance, power consumption, delay and reliability faced by the complex system on chip (SoC), and propose a kind of double-layer double-ring type on-chip with fair routing and bandwidth that can be space-division multiplexed. Network Topology

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