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Test structure artwork forming method and system, and test structure forming method

A technology for testing structure and layout, applied in special data processing applications, instruments, electrical and digital data processing, etc., can solve problems such as low efficiency, and achieve the effect of simplifying testing procedures, simple patterns, and reducing open circuits

Active Publication Date: 2011-05-11
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, in the method for forming the test structure, it is necessary to form a plurality of test structure patterns between the plurality of lead pad patterns, and connect the test structure patterns to the corresponding lead pad patterns, which is less efficient.

Method used

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  • Test structure artwork forming method and system, and test structure forming method
  • Test structure artwork forming method and system, and test structure forming method
  • Test structure artwork forming method and system, and test structure forming method

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Embodiment Construction

[0073] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0074] In the design of semiconductor integrated circuits, it is often necessary to form a test structure to verify whether the designed device and the manufacturing process of the device meet the requirements.

[0075] The present invention provides a method for forming a test structure layout, comprising forming at least two dummy wire pad patterns, and arranging the dummy wire pad patterns according to the layout of the wire pad patterns, and the dummy wire pad patterns The size and spacing are the same as the actual lead pad pattern.

[0076] Next, form a virtual frame pattern that frames at least two of the dummy lead pad patterns, and the virtual frame pattern is used to divide the area of ​​a single test structure pattern to form a frame of a standard unit.

[0077] Then, a single test structure pattern is formed between the dummy ...

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PUM

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Abstract

A formation method for test structural layout comprises: forming at least two virtual lead wire welding pad patterns; forming a virtual frame pattern containing the virtual lead wire welding pad patterns; forming single test structure patterns among the virtual lead wire welding pad patterns of the virtual frame parameter, connecting the single test structure pattern with the virtual lead wire welding pad patterns to form a standard unit pattern containing the virtual frame, the virtual lead wire welding pad patterns and the single test structure patterns; forming lead wire welding pad patterns; forming a frame pattern containing the lead wire welding pad patterns; inserting the standard unit pattern into the frame pattern, and aligning the virtual lead wire welding pad patterns of the standard unit pattern to the lead wire welding pad patterns of the frame pattern, to form a test structural layout. The invention provides a system forming test structural layouts, a formation method of test structures and a formation method of layouts. The invention can improve the efficiency of layout formation, save time and reduce error rate.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method and system for forming a layout of a test structure, and a method for forming a test structure. Background technique [0002] In the layout design and manufacturing process of semiconductor integrated circuits, test structures are often required to verify the quality of the design and manufacturing process. For example, Chinese patent No. ZL200620046824.3 discloses a metal-insulator-metal radio frequency test structure. , so that it forms a form of resistance parallel connection during testing, thereby greatly reducing the resistance value of the metal-insulator-metal capacitor and improving the value of the quality factor. [0003] The test structure is the same as the structure of the device, which is also formed through the processes of circuit design, layout design, layout decomposition, and device manufacturing. If a defect occurs during the layout design s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50H01L21/00
Inventor 陆黎明龚斌胡轶强
Owner SEMICON MFG INT (SHANGHAI) CORP
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