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Forming method of shallow groove isolation structure

A technology of isolation structures and shallow trenches, which is applied in the fields of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., and can solve problems affecting the performance of semiconductor devices and the isolation performance of shallow trench isolation structures

Inactive Publication Date: 2011-01-12
SEMICON MFG INT (SHANGHAI) CORP
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  • Claims
  • Application Information

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Problems solved by technology

[0009] In the prior art, during the formation of shallow trenches, due to the reaction between etching gas and silicon in the semiconductor substrate, polymers are produced on the sidewalls of the shallow trenches, which affects the isolation performance of the shallow trench isolation structure, thereby affecting the performance of the semiconductor device. performance

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  • Forming method of shallow groove isolation structure
  • Forming method of shallow groove isolation structure
  • Forming method of shallow groove isolation structure

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Embodiment Construction

[0020] The invention introduces the gas reacting with the polymer to remove the residual polymer without affecting the side wall of the shallow trench, so that the finally formed shallow trench isolation structure is complete.

[0021] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0022] Figure 5 It is a flowchart of a specific embodiment of forming a shallow trench isolation structure in the present invention. Such as Figure 5 As shown, step S101 is performed to provide a semiconductor substrate with a pad oxide layer and an etch barrier layer in sequence, and the etch barrier layer has an opening that penetrates the etch barrier layer and exposes the pad oxide layer; executes step S102 to corrode the barrier layer As a mask, etch the pad oxide layer and the semiconductor substrate along the opening to form a shallow trench, wherein the sidewall of the shallow trench has a polymer; perf...

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Abstract

A method for forming a shallow trench isolation structure comprises steps of providing a semiconductor substrate equipped with a pad oxide layer and a corrosion barrier layer sequentially, wherein the corrosion barrier layer is provided with an opening which penetrates through the corrosion barrier layer and is exposed to the pad oxide layer, utilizing the corrosion barrier layer as a mask, etching the pad oxide layer and the semiconductor substrate along the opening to form a shallow trench, wherein the lateral wall of the shallow trench is provided with polymer, leading into gas which is reacted with polymer, removing residual polymer, filling an insulating oxide layer in the shallow trench, removing the corrosion barrier layer and the pad oxide layer, and forming the shallow trench isolation structure. The invention leads the gas which is reacted with the polymer, removes the residual polymer, does not affect the lateral wall of the shallow trench, and enables the shallow trench isolation structure formed finally to be complete.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a shallow trench isolation structure. Background technique [0002] As the size of integrated circuits decreases, the devices that make up the circuits must be placed more densely to fit the limited space available on the chip. Since current research is devoted to increasing the density of active devices per unit area of ​​a semiconductor substrate, effective insulating isolation between circuits becomes more important. The methods for forming isolation regions in the prior art mainly include local oxidation isolation (LOCOS) process or shallow trench isolation (STI) process. The LOCOS process is to deposit a layer of silicon nitride on the surface of the wafer, and then perform etching to oxidize and grow silicon oxide in part of the recessed area, and the active device is generated in the area determined by the silicon nitride. For isolation techno...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
Inventor 陈海华黄怡张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP