FPGA implementing method for Turbo product code optimized encoding and decoding algorithm

An implementation method and product code technology, applied in the field of forward error correction coding and decoding, can solve the problems of cumbersome configuration, simplified algorithm, poor flexibility, etc., and achieve the effects of flexible configuration, high coding performance, and high data rate

Active Publication Date: 2009-07-15
CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In addition, most of the existing TPC solutions are various special-purpose ICs and various high-speed signal communication instruments, which are expensive to use, inconvenient to use, and poor in flexibility.
The configuration of IP core (IP core) is cumbersome, the cost is relatively high, or the algorithm is too simplified, the performance is not high, and because there is no core code, it cannot be modified independently according to the development needs

Method used

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  • FPGA implementing method for Turbo product code optimized encoding and decoding algorithm
  • FPGA implementing method for Turbo product code optimized encoding and decoding algorithm
  • FPGA implementing method for Turbo product code optimized encoding and decoding algorithm

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Embodiment Construction

[0040] Such as figure 2 Shown, a kind of FPGA implementation method of Turbo product code optimization coding algorithm, comprises the following steps:

[0041] 1) Encoding:

[0042] Use Ram1, Ram1 two random access memory (Random Access Memory, RAM) and output Ram, after the coded data transmission starts, the data is written into Ram1. When Ram1 is full (the length of 1 information block), start to write to Ram2 and at the same time the encoder starts to work, the encoder reads line by line from Ram1 for line encoding, writes to the output Ram, that is, writes image 3 The input matrix (inputarray) and the row parity bit (parity check 1 bit); after all the rows are encoded, they are encoded column by column and written to the output Ram, that is, written image 3The column parity bit (2 bits of parity) and the parity bit of the parity bit (2 bits of parity). After reading Ram1, that is, after reading the information of 1 information block length, wait for Ram2 to be full...

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Abstract

An FPGA realization method for optimizing coding / decoding algorithm with Turbo product code comprises the following steps: 1) coding, after the data to be coded is transmitted to a random access memory, reading in by the coder from the random access memory line by line or row by row, executing lien or row coding with Turbo product code, after line coding or row coding is finished, coding row by row or line by line, writing the coded data into an output Ram, when the output Ram is full, outputting frame header, then reading out the whole block of data in the output Ram, complementing the clock gap from the completion of data output to the output of next data block; and shortening the information bit according to the requirement of code rate; 2) framing, framing and transmitting the output data after coding; and 3) decoding, de-framing and decoding the received data. The invention can be flexibly configured for aiming at different application requirements. A higher data speed can be obtained through parallel using a plurality of decoding units. The FPGA realization method can be used for high-speed data transmission.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to forward error correction coding and decoding technology in information transmission, and is a new FPGA implementation method of TPC coding and decoding algorithm. Background technique [0002] In data communication, channel coding and decoding is one of the core components of the communication system, and it is committed to providing higher transmission reliability for the system. Turbo product code (Turbo Product Code, referred to as TPC) encoding and decoding technology is an error control technology developed in the past ten years. Composed of new coding techniques. TPC has a very good error correction ability, not only greatly improves the system performance in the additive white Gaussian noise channel (AWGN), but also greatly improves the system performance in the Rayleigh fading channel (Rayleigh Fading Channel). [0003] TPC is a product code, and its basic struct...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/47G06F17/50H04L1/00
Inventor 牛韬李裕丁勇飞沈凯虹石吉利徐丁海
Owner CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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