Exponent cut LFSR replanting VLSI test data compression method

A technology of test data and compression method, applied in the direction of measuring electricity, measuring device, measuring electrical variables, etc., can solve the problems of few chip test points, large amount of test data, incompatibility, etc., to reduce data length and improve coding efficiency Effect

Inactive Publication Date: 2009-07-29
HEFEI UNIV OF TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input/output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.
[0004] 2. The automatic test equipment ATE is expensive, and the development speed of chip design and manufacturing technolog...

Method used

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  • Exponent cut LFSR replanting VLSI test data compression method
  • Exponent cut LFSR replanting VLSI test data compression method
  • Exponent cut LFSR replanting VLSI test data compression method

Examples

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Embodiment Construction

[0030] Implement the present invention and carry out as follows:

[0031] a. Carry out pseudo-random test to the circuit under test, and use the fault simulation tool to determine the untested faults, and then use the automatic test pattern generation tool (ATPG) to generate a certain test set T for the untested faults;

[0032] b. Carrying out test vector concatenation on the test set T, the concatenation is to connect the tail of the previous test vector to the head of the next test vector, and form a test sequence T after concatenating all the test vectors 2 ;

[0033] c. The test sequence T to be formed 2 According to the constant k segmentation, the segmentation strategy is to make the number of certain bits contained in each segment equal to or less than and closest to a certain constant k after segmentation. The specific method is to start from the test sequence T 2 Take a subsequence of length m at the beginning of sequentially calculated from T 2 The length of th...

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Abstract

The invention provides a method for compressing power-number-slit LFSR reseeding VLSI testing data, which is characterized in that: after the testing vector is cascaded, the segmentation is carried out according to the positioning number so that the length of each segment is just the power number of two; furthermore, the positioning number contained by each segment is equal to or less than and mostly approaching to a determinate constant k; subsequently, the compressing is carried out by a linear feedback shift register LFSR. The method is a non-invading data compressing testing method and requires no change of the structure of the circuit to be tested, in particular to the structure of the scanning chain in the circuit; furthermore, memory capacity required for data testing is reduced and the testing application time is shortened.

Description

technical field [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-in self-test (Built-InSelf-Test) method for a VLSI. Background technique [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in a chip, and can integrate pre-designed and verified IP cores, such as memory cores, microprocessor cores, DSP cores, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system on chip or system chip SOC. SOC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market. However, the testing of SOC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / out...

Claims

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Application Information

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IPC IPC(8): G01R31/3183
Inventor 梁华国詹文法王保青蒋翠云黄正峰易茂祥欧阳一鸣陈田李扬刘军孙科
Owner HEFEI UNIV OF TECH
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