Exponent cut LFSR replanting VLSI test data compression method

Abstract

The invention provides a method for compressing power-number-slit LFSR reseeding VLSI testing data, which is characterized in that: after the testing vector is cascaded, the segmentation is carried out according to the positioning number so that the length of each segment is just the power number of two; furthermore, the positioning number contained by each segment is equal to or less than and mostly approaching to a determinate constant k; subsequently, the compressing is carried out by a linear feedback shift register LFSR. The method is a non-invading data compressing testing method and requires no change of the structure of the circuit to be tested, in particular to the structure of the scanning chain in the circuit; furthermore, memory capacity required for data testing is reduced and the testing application time is shortened.

Description

technical field [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-in self-test (Built-InSelf-Test) method for a VLSI. Background technique [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in a chip, and can integrate pre-designed and verified IP cores, such as memory cores, microprocessor cores, DSP cores, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system on chip or system chip SOC. SOC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market. However, the testing of SOC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / out...

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Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input / output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. The automatic test equipment ATE is expensive, and the development speed of chip design and manufacturing technology is faster than that of ATE. The clock frequency of the chip has exceeded the frequency of the most advanced ATE at present, and full-speed testing cannot be performed.

[0005] 3. The amount of test data is large. The more cores integrated in the SOC, the greater the amount of test data required

However, these solutions are incompatible with the standard scan design flow, and the structure of the scan chain needs to be restructured, which is very costly

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