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Semiconductor memory device

一种存储装置、半导体的技术,应用在信息存储、静态存储器、只读存储器等方向,达到简化电路结构、缩短测试时间、减小电路规模的效果

Active Publication Date: 2009-08-05
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] However, when testing, V SS (V SS = 0, the voltage is below 0V), so when the threshold voltage Vth is a negative potential, it is impossible to use the same test method as the positive potential for the traditional circuit structure

Method used

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  • Semiconductor memory device
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Experimental program
Comparison scheme
Effect test

no. 1 approach

[0054] refer to figure 2 The semiconductor memory device of the first embodiment will be described. figure 2 is a block diagram showing a configuration example of the semiconductor memory device of this embodiment.

[0055] In the case of the first embodiment, such as figure 2 As shown, the determination level changing circuit 3 is configured as a reference current control circuit 4 .

[0056] When the test signal T1 is not input, the reference current control circuit 4 supplies the constant current output from the constant current circuit 1 as the reference current Iref to the memory cell M via the Y switch 103. On the other hand, when the test signal T1 is input , through the control signal S, the current value of the reference current Iref is changed to a current value larger than the constant current, and the changed current value is used as the reference current Iref and supplied to the memory unit M through the Y switch 103 .

[0057] As already explained, in the m...

no. 2 approach

[0109] refer to Figure 7 A semiconductor memory device according to a second embodiment will be described. Figure 7 It is a block diagram showing a configuration example of this embodiment. for with figure 2 The same structures as in the first embodiment are assigned the same symbols, and description thereof will be omitted.

[0110] In the case of the second embodiment, such as Figure 7 As shown, the determination level changing circuit 3 is configured as a reference voltage control circuit 5 .

[0111] When the reference voltage control circuit 5 is not input with the test signal T1, it outputs the constant voltage output from the constant voltage circuit 2 as the reference voltage Vref to the - side terminal of the comparator 107. On the other hand, when the test signal T1 is input, In this case, the current value of the reference voltage Vref is changed with respect to the constant voltage by the control signal S, and the adjusted reference voltage Vref is output t...

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Abstract

Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When a test signal is input, the semiconductor memory device changes from a normal mode to a test mode for evaluating characteristics of the plurality of memory cells. The semiconductor memory device also includes: a memory cell selecting portion for selecting a memory cell; a constant voltageportion for generating a reference voltage; a constant current portion for generating a reference current; an X switch voltage switching control circuit for supplying one of an X selection signal anda voltage signal input from an external terminal to a gate of the memory cell; a Y switch portion for supplying the reference current to a drain of the memory cell selected by a Y selection signal; acomparator for detecting whether or not a drain voltage that is a voltage of the drain has exceeded the reference voltage; and a decision level changing portion for adjusting a current value of the reference current and a voltage value of the reference voltage so as to change a decision level of the comparator based on a control signal in the test mode.

Description

technical field [0001] The present invention relates to a semiconductor memory device provided with an electrical measurement function capable of directly measuring the characteristics of nonvolatile memory cells such as EEPROM and ROM in which data can be written and erased by electrical manipulation from the outside. Background technique [0002] Conventionally, in evaluating the characteristics of memory cells in a nonvolatile semiconductor memory device such as an EEPROM, each memory cell in the semiconductor memory device is directly measured from the outside. [0003] For example, in the case of EEPROM, in the case of erasing data in the memory cell M, and in the case of writing data in the memory cell M, when evaluating electrical characteristics such as the threshold voltage Vth of the memory cell M in various states, such as Figure 10 (data erasure) or Figure 11 As shown in "Data Writing", it is set that the gate of the memory cell M can be changed arbitrarily fro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/00G11C16/06
CPCG11C16/04G11C29/50004G11C29/50G11C16/34G11C29/00G11C16/30G11C16/08
Inventor 佐藤丰宇都宫文靖冈智博
Owner SII SEMICONDUCTOR CORP
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