Method for restraining mid-point potential excursion of three-phase four-bridge arm tri-level inverter

Abstract

The invention discloses a method for rejecting the central potential drift of a three-phase four-bridge arm three-level inverter. The SVPWM vector of the three-phase four-bridge arm three-level inverter is reduced from the traditional three-dimension to a plane, the switch statuses of the first three bridge arm and the fourth bridge arm are separately selected, the vector table of the first three bridge arm three-level space is made full use of to select a zero vector and a length vector, small vectors are used in pairs while mid-sized vectors can not be used directly, neighboring vectors are combined into mid-sized vectors, and the switch status of the fourth bridge arm is selected according to the principle of the offset between the charge effect and the discharge effect of a capacitor. The algorithm is simple and easy to be realized, and can not only contain asymmetric load but also realize that the average value of the current which passes through the neutral point of a DC (direct current) side capacitor is strictly being zero under any load power factors and modulation ratio, thus effectively rejecting the drift of neutral point potential. No sample current is required in the algorithm, thus reducing the requirement of the system to the neutral point of the DC side capacitor. An open-loop control and a closed-loop control are respectively available.

Description

technical field [0001] The invention relates to a method for suppressing midpoint potential drift of a three-level inverter, in particular to a method for suppressing midpoint potential drift of a three-phase four-arm three-level inverter. Background technique [0002] With the rapid development of power electronics technology and computer technology, inverters are widely used in high-power fields. Therefore, multi-level technology has gradually become a hot research direction. Traditional multi-level topologies can be divided into capacitor-clamped, diode-clamped, and cascaded, among which the diode-clamped topology has attracted widespread attention due to its simple structure. Using multi-level technology can reduce the voltage drop of each power tube, thereby increasing the system power, reducing the harmonic content of the output voltage, reducing electromagnetic interference, and improving the stability of the system; however, as the number of levels increases , the c...

AI Technical Summary

Problems solved by technology

At present, scholars at home and abroad have researched a variety of algorithms based on the three-phase three-leg three-level topology, but most of them focus on "reducing" the midpoint potential drift, and the suppression effect is closely related to the power factor and modulation ratio of the load.

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