Loading/memorizing unit of embedded processor

Abstract

The invention provides a loading / memorizing unit of an embedded processor; in the loading / memorizing unit, an entire pipeline moe is adopted to read and write command to visit high-speed cache on the disc; if the visit absence occurs in a preorder command, the command resulting in the visit absence is memorized in a special visit absence buffer, the pipeline resource is released and the sequent command continues to visit the high-speed cache; an independent update buffer outside the disc is arranged to cache the write operation of a memory outside the disc to cause the fast retirement of the write operation of the memory outside the disc; an independent update buffer on the disc is arranged to cache the high-speed cache update operation on the disc to cause the fast retirement of the high-speed cache write operation. When the high-speed cache visit absence occurs, the invention can not block the pipeline, thus improving the performance of the processor.

Description

technical field [0001] The invention relates to a load / store unit of an embedded processor. Background technique [0002] In recent years, with the development of high-performance embedded processors, in order to improve the utilization of internal logic components and improve the performance of the entire processor, various methods such as multi-instruction launch and out-of-order execution are usually adopted. Some superscalar processors that are commonly used today can usually execute multiple instructions concurrently in one instruction cycle. After the processor prefetches a batch of instructions from the instruction cache, it will analyze those instructions that can be executed in parallel without associativity, and then send them to several independent execution units for parallel execution. [0003] Generally speaking, load / store instructions (executed by the load / store unit) require multiple instruction cycles, while general arithmetic instructions are usually exec...

AI Technical Summary

Problems solved by technology

However, due to the existence of cache access misses, once access misses occur, data loading / storage needs to be loaded / stored from the off-chip memory through an external bus. This process requires several or even dozens of instruction cycles.

Since the current mainstream embedded high-performance processors generally adopt a pipeline structure, the pause of the previous instruction will block the normal execution of the entire pipeline.

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