Shift register and liquid crystal display grid electrode driving device

A technology of shift register and liquid crystal display, which is applied in the direction of static memory, static indicator, digital memory information, etc., can solve the problems of threshold voltage shift, reduce the reliability of shift register, affect the life of shift register, etc., and achieve the purpose of suppressing Output noise, the effect of ensuring normal working life

Active Publication Date: 2009-10-14
K TRONICS (SUZHOU) TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If there are a total of 1000 rows of liquid crystal pixels, and one shift register controls a row of thin film transistors, each shift register is only in the working state for T/1000 of the time T/1000 of the time when the liquid crystal display displays a frame of image, and mo

Method used

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  • Shift register and liquid crystal display grid electrode driving device
  • Shift register and liquid crystal display grid electrode driving device
  • Shift register and liquid crystal display grid electrode driving device

Examples

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Embodiment Construction

[0054] Such as Figure 5 Shown is a schematic structural diagram of the first embodiment of a shift register of the present invention. The shift register includes: thin film transistors T301, T302, T303, T304, T111 and a pull-down thin film transistor driving unit 1. The drain of T301 and the first clock signal input terminal (CLKIN) connection, the gate is connected to the pull-down thin film transistor driving unit 1 and one end of the capacitor C301, the source is connected to the other end of C301 and the signal output terminal (OUTPUT); the drain of T302 is connected to the source of T301, The gate is connected to the reset signal input terminal (RESETIN), the source is connected to the low voltage signal input terminal (VSSIN); the drain and gate of T303 are both connected to the signal input terminal (INPUT); the drain of T304 is connected to the source of T303 The gate is connected to the reset signal input terminal (RESETIN), the source is connected to the low voltage sig...

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PUM

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Abstract

The invention relates to a shift register and a liquid crystal grid electrode driving device. The shift register comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a down-pulled thin film transistor and a down-pulled thin film transistor driving unit; the drain electrode of the down-pulled thin film transistor is respectively connected with a signal output end and the source electrode of the first thin film transistor; the source electrode of the down-pulled thin film transistor is connected with a low-voltage signal input end; and the down-pulled thin film transistor driving unit is used for controlling the opening of the down-pulled thin film transistor when a signal output by the signal output end is in low level and a signal input by a first clock signal input end is in high level. The shift register and the liquid crystal grid electrode driving device can effectively inhibit the output noise and ensure that all the thin film transistors therein can not be prone to large threshold voltage deviation, thereby having normal working life.

Description

Technical field [0001] The invention relates to the field of liquid crystal display, in particular to a shift register and a gate driving device of a liquid crystal display. Background technique [0002] In the existing shift register, the typical structure is Thomson's four-transistor two-capacitor structure. figure 1 Shown is a schematic diagram of the shift register structure, figure 2 Shown as figure 1 The input and output timing diagram of the shift register shown. The working principle is: select figure 2 Show a part of the timing diagram and divide it into five stages. In the first stage, the input signal at the signal input terminal (INPUT) is high, and the input signal at the reset signal input terminal (RESETIN) is low, and the transistor T103 Turned on, the transistor T104 is turned off, so the node PU is also charged by the transistor T103 at a high level; in the second stage, the input signal at the signal input terminal (INPUT) is at low level, and the reset sig...

Claims

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Application Information

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IPC IPC(8): G11C19/28G09G3/36
Inventor 商广良
Owner K TRONICS (SUZHOU) TECH CO LTD
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