Shift register and grid drive set of liquid crystal display

Abstract

The invention relates to a shift register and a grid driver set of a liquid crystal display. The shift register comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first pull-down thin film transistor, a second pull-down thin film transistor, a first pull-down thin film transistor drive unit and a second pull-down thin film transistor drive unit, wherein the first pull-down thin film transistor drive unit is used for controlling the first pull-down thin film transistor to open when a signal output end outputs a low level and a first clock signal input end inputs a high level; and the second pull-down thin film transistor drive unit is used for controlling the second pull-down thin film transistor to open when the signal output end outputs a low level and a second clock signal input end inputs a high level. The shift register and the grid drive set of a liquid crystal display can effectively restrain output noise and can ensure that the shift register and each thin film transistor in the grid drive set can not generate great threshold voltage excursion, thereby ensuring the normal service life of the shift register and the grid drive set.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to a shift register and a gate driving device of a liquid crystal display. Background technique [0002] In the existing shift register, the typical structure is Thomson's four-transistor two-capacitor structure, figure 1 Shown is a schematic diagram of the structure of Thomson's four-transistor two-capacitance shift register. figure 2 shown as figure 1 The input and output timing diagram of the shift register shown, the specific principle is: select figure 2 Part of the timing diagram shown and divided into five stages, in the first stage, the signal input terminal (INPUT) input signal is high level, the reset signal input terminal (RESETIN) input signal is low level, transistor T103 It is turned on, and the transistor T104 is cut off, so the charging of the node PU through the transistor T103 is also high level; in the second stage, the input signal of the signal input t...

AI Technical Summary

Problems solved by technology

If there are a total of 1000 rows of liquid crystal pixels, and one shift register controls a row of thin film transistors, each shift register is only in the working state for T / 1000 of the time T / 1000 of the time when the liquid crystal display displays a frame of image, and most of the rest of the time In the non-working state, the transistors T202 and T204 are biased by almost DC, which will cause a large threshold voltage shift of T202 and T204, which reduces the reliability of the shift register and will eventually affect the shift register. life

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