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Method for improving wafer-stage electromigration performance test

An electromigration, wafer-level technology, applied in the direction of single semiconductor device testing, semiconductor/solid-state device testing/measurement, etc., can solve the problems of equipment hardware damage, device burnout, etc., and achieve the effect of reducing damage

Inactive Publication Date: 2012-05-30
HEJIAN TECH SUZHOU
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Problems solved by technology

[0004] In view of the defects of the above-mentioned existing testing methods, the purpose of the present invention is to propose a method for improving wafer-level electromigration performance testing, so as to solve the problem of equipment hardware damage and device failure in the wafer state caused by unreasonable machine test procedures. Burn out

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  • Method for improving wafer-stage electromigration performance test
  • Method for improving wafer-stage electromigration performance test

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Embodiment Construction

[0021] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, below in conjunction with a preferred embodiment of the present invention, the detailed description is as follows:

[0022] Specifically, the testing process of electromigration stability for devices in the wafer or wafer state is roughly divided into three stages:

[0023] The first is the initial resistance measurement stage: at room temperature, measure the resistance with a small current to determine whether the structure is the one expected to be tested;

[0024] Then there is the current step stage: the resistance is heated by increasing the current, and the temperature reached by the resistance under a certain current is estimated by the actual measured resistance value and the temperature coefficient of resistance.

[0025] The last stage is the constant power stage: when the resistance reaches the preset test temperature, record t...

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Abstract

The invention discloses a method for improving wafer-stage electromigration performance test, which aims at solving the equipment hardware damage and device damage under a wafer state due to an unreasonable test program of an original machine. The method comprises the following steps: using a test system with a machine model of Agilent 4070, respectively connecting both ends of a measuring probe with a current-voltage source and a port of an object to be tested and measuring input current and load-end voltage to obtain the electromigration performance of a device in the wafer state. The methodfor improving wafer-stage electromigration performance test is characterized in that voltage limiting and current limiting are added in the test program of the machine to limit the voltage of the measuring probe at the current input end within a measuring range of the current-voltage source at the voltage measuring end; and a control command is added to exit the test when the power exceeds a rated value. The method for improving wafer-stage electromigration performance test effectively avoids melting, scorching and aluminum-sintering phenomena on the tip of the measuring probe and lightens the damage of the wafer-shaped device caused by the machine hardware damage.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an improved method capable of effectively avoiding damage to hardware and wafers that occurs during detection by testing equipment. Background technique [0002] In the wafer process, testing the device in the wafer state and obtaining its electromigration characteristic parameters is an essential and important link for the subsequent process. Due to the outstanding advantages of stability and accuracy, the test system of the model "Agilent 4070" produced by Agilent is generally used in the industry to test the wafer parameters of products. [0003] However, the EMiso test method provided in EIA JESD-61 according to the standard number of the World Electrical Industry Association only generally stipulates the test process and parameter setting range. In the actual test process, under the theoretically feasible parameter settings, the test equipment is often damaged, re...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66G01R31/26
Inventor 彭昶
Owner HEJIAN TECH SUZHOU