Dual-bus visual processing chip architecture

Abstract

The invention relates to the field of structural design of visual information processing chips in integrated circuits, and discloses dual-bus visual processing chip architecture. The architecture comprises a first bus, a second bus, a visual computing and deciding module connected to the first bus, a first memory connected to the first bus, a characteristic combination and mode generating module connected to the second bus, an image characteristic extraction module connected to the second bus, a second memory connected to the second bus, and a bridge circuit for connecting the first bus and the second bus.

Description

technical field [0001] The invention relates to the field of structural design of visual information processing chips in integrated circuits, in particular to a dual-bus visual processing chip architecture. Background technique [0002] With the development of large-scale integrated circuit design, System on a Chip (SoC) technology emerges as the times require. IP core (Intellectual Property, IP) multiplexing is an important way to realize SoC. Among them, the on-chip bus is the key technology of IP core interconnection. Its proposal effectively solves the problems of IP core transplantation reuse and system design verification. For vision processing chips, how to combine machine vision with small-volume, low-power-consumption hardware systems to design vision chips with visual perception and image processing functions is currently a research hotspot in the field of vision and intelligent information processing. [0003] According to the characteristics of vision processi...

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Problems solved by technology

[0004] To sum up, the current vision processing chip structure mainly has the following problems: insufficient memory bandwidth, poor scalability, low average communication efficiency, single clock, etc., which cannot well meet the requirements of actual vision processing

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