Encapsulating structure and encapsulating method of chip

Abstract

The invention relates to an encapsulating structure of a chip, which comprises a chip holding shelf, the chip, an encapsulating body, a plurality of patterning metal line sections, a plurality of patterning protective layers, a plurality of patterning UBM layers and a plurality of conducting elements, wherein the chip holding shelf is provided with a chip holding area, the front face of the chip holding area is provided with an adhesion layer; the active face of the chip is provided with a plurality of weld pads, and the back face of the chip is formed on the adhesion layer of the chip holding shelf; the encapsulating body is covered around the chip holding shelf provided with the chip and exposes the weld pads on the active face of the chip, and the height of the encapsulating body is larger than that of the chip; one end of the patterning metal line section is electrically connected with the weld pads, and the other end extends outside and is covered on one surface of the encapsulating body; the patterning protective layers are covered on the patterning metal line sections and expose the part of a surface of a fan-out structure formed in such a way that the patterning metal line sections extend outside the active face of the chip; the patterning UBM layers are respectively formed on the part of the surface of each fan-out structure and electrically connected with the patterning metal line sections; and the conducting elements are electrically connected with the patterning metal line sections by the UBM layers.

Description

technical field [0001] The invention relates to a packaging method for chip reconfiguration, in particular to a packaging method for chip reconfiguration using a chip holder. Background technique [0002] Semiconductor technology has developed quite rapidly, so the miniaturized semiconductor grain (Dice) or chip (chip) must have diversified functional requirements, so that the semiconductor chip must be configured with more inputs in a small area / output pads (I / O pads), thus making the density of metal pins (pins) also increase rapidly. Therefore, the early lead frame packaging technology is no longer suitable for high-density metal pins; therefore, a ball array (Ball Grid Array: BGA) packaging technology has been developed. The ball array package has the advantage of higher density than the lead frame package. In addition, its solder balls are less prone to damage and deformation. [0003] With the popularity of 3C products, such as: mobile phone (Cell Phone), personal ...

AI Technical Summary

Problems solved by technology

This thinned chip is reconfigured on another substrate, and then multiple chips are formed into a package by injection molding; because the chip is very thin, the package is also very thin, so when the package is detached After the substrate, the stress of the package itself will cause the package to warp, increasing the difficulty of the subsequent cutting process

[0006] In addition, after the wafer is diced, when it is reconfigured on another carrier, because the size of the new carrier is larger than the original size, it will not be aligned in the subsequent ball planting process, and the reliability of the package structure will be reduced.

[0007] In addition, during the entire packaging process, there will also be a problem that the manufacturing equipment will generate excessive local pressure on the chip during ball planting, which may damage the chip; at the same time, it may also be caused by the material of the ball planting. The resistance value between the pads becomes larger, which affects the performance of the chip and other issues

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