Grid and formation method thereof

Abstract

A grid formation method comprises the following steps: forming a polysilicon layer on a substrate; executing first etching operation on the polysilicon layer and executing second etching operation on the polysilicon layer by etching gases containing bromine-based gases to form the grid; if the flow of the pumped bromine-based gases is a0 when the grid perpendicular to the substrate is obtained, the flow a when the bromine-based gases are pumped is more than a0. A grid is formed on the substrate and comprises the polysilicon layer; wherein, the polysilicon layer comprises a top wall, a bottom wall opposite to the top wall and a side wall jointed with the top wall after extending upwards from the edge of the bottom wall; the included angle of at least partial side wall and the bottom wall is less than 90 degrees. Under the condition of keeping the electrical length of a channel unchanged, the overlapped region of the grid and a drain is expanded and the hot carrier effect is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a gate and a forming method thereof. Background technique [0002] In the semiconductor manufacturing process, increasing demands continue to push the semiconductor manufacturing process towards the direction of high integration and low power consumption. However, as the size of the chip decreases, the power supply voltage and operating voltage of the chip do not decrease a lot accordingly, so the corresponding electric field strength increases, resulting in an increase in the movement rate of electrons. When high-energy electrons collide with the crystal lattice, the lattice atoms will be ionized to generate electron and hole pairs. Part of the electrons can change the direction of motion due to scattering, and can overcome the barrier of the oxide layer and enter the gate oxide layer, resulting in a device The electrical parameters degenerate, this effect i...

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Problems solved by technology

[0005] However, when applying the above-mentioned traditional methods to improve the hot carrier effect, there are more or less disadvantages

For example, when phosphorus-doped drain region is selected, in order to make the resistance of source and drain relatively small, the dose of phosphorus implanted must be above 1E15, so the Isub of the device is an order of magnitude smaller than that of arsenic implanted; when double-diffused drain region is selected, it is difficult A shallow junction is formed, so the effect on reducing Emax is limited; when the method of improving the lightly doped drain region is selected, due to the introduction of the n-region, the LDD structure will also increase the series resistance, resulting in a decrease in the driving current; resulting in LDD's The process parameters must be carefully optimized to obtain the best device performance; when choosing the method of reducing the supply voltage, considering the compatibility issue, the voltage cannot be completely reduced synchronously with the reduction of the line width, which makes the hot carrier effect limited improvement

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