Source switch-type charge pump applied to phase lock loop
A switch type, charge pump technology, applied in the direction of electrical components, automatic power control, etc., can solve problems such as dynamic mismatch, achieve the effects of reducing speed mismatch, improving frequency purity, and improving dynamic matching performance
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specific Embodiment approach 1
[0025] Specific implementation mode one: combine image 3 Describe this embodiment. This embodiment includes a bias circuit 1, a charge current circuit 2, a discharge current circuit 3, a charge current shutdown acceleration circuit 4, a discharge current shutdown acceleration circuit 5, and a speed compensation capacitor C slowNThe first bias voltage VbP1 output terminal of the bias circuit 1 is connected to the first bias voltage VbP1 input terminal of the charging current circuit 2; the first input terminal A of the bias circuit 1 and the second bias voltage of the charging current circuit 2 The input terminals are both the second bias voltage VbP2 input terminals; the second input terminal B of the bias circuit 1 and the first bias voltage input terminals of the discharge current circuit 3 are both the third bias voltage VbN1 input terminals; the bias circuit The third input terminal C of 1 and the second bias voltage input terminal of the discharge current circuit 3 are b...
specific Embodiment approach 2
[0026] Specific implementation mode two: combination Figure 4 Describe this embodiment, the difference between this embodiment and the specific embodiment is that the charging current circuit 2 includes a first PMOS transistor MP1, a second PMOS transistor MP2 and a third PMOS transistor MP3; the gate of the first PMOS transistor MP1 is a charging control signal UP input terminal, the source of the first PMOS transistor MP1 is the power input terminal, the drain of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2, and the gate of the second PMOS transistor MP2 is connected to the first Bias voltage VbP1 output terminal, the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3 and the acceleration signal output terminal of the charging current shutdown acceleration circuit 4, the gate of the third PMOS transistor MP3 is the second bias The input terminal of the voltage VbP2 is set, and the...
specific Embodiment approach 3
[0027] Specific implementation mode three: combination Figure 4 Describe this embodiment, the difference between this embodiment and the specific embodiment is that the discharge current circuit (3) includes a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3; the gate of the first NMOS transistor MN1 is a discharge current circuit. The control signal DN input terminal, the source of the first NMOS transistor MN1 is connected to the power ground, the drain of the first NMOS transistor MN1 is connected to the source of the second NMOS transistor MN2, and the gate of the second NMOS transistor MN2 is the third bias voltage VbN1 The input terminal, the drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3 at the same time, the discharge current turns off the acceleration signal output terminal of the acceleration circuit 5 and the speed compensation capacitor C slowN One end of the speed compensa...
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