Clock data recovery circuit, method and test device utilizing them

Abstract

A change point detection circuit (16) extracts a clock signal (S3) from an input data, i.e. a serial data (S1). A variable delay circuit (40) imparts a delay dependent on a delay control signal (S8a)to a reference signal (S4) having a predetermined frequency, and shifts the phase of the reference signal (S4) with reference to an initial delay. An input latch circuit (14) latches internal serial data (S2) using the output signal from the variable delay circuit (40) as a strobe signal (S5). A phase comparator (22) matches the frequencies of the clock signal (S3) and the strobe signal (S5) and generates phase difference data (S9) dependent on the phase difference of two signals. A loop filter (30) integrates the phase difference data (S9) generated by the comparator (22) and outputs the delay control signal (S8a). A phase shift amount acquisition section (50) acquires the amount of phase shift with reference to the initial delay imparted to the reference signal by the variable delay circuit (40) based on the delay control signal (S8a).

Description

technical field [0001] The invention relates to a clock data recovery technique for regenerating input bit stream data by using a strobe signal. Background technique [0002] In order to use few data transmission lines to send and receive data between semiconductor circuits, serial data transmission is adopted. Serial data transmission can adopt CDR (Clock and Data Recovery: clock data recovery) mode or source synchronous (Source Synchronous) mode. In the CDR method, 8B10B encoding or 4B5B encoding is used so that serial data does not continuously take the same value over a predetermined period, and a clock signal for synchronization is embedded in the serial data. [0003] When testing a semiconductor circuit that outputs serial data as a device under test (DUT), a CDR circuit is provided in an input stage of a semiconductor test device (also simply referred to as a test device). The CDR circuit extracts the reference clock signal from the serial data, and generates a str...

AI Technical Summary

Problems solved by technology

However, the following problems were recognized: when using a CDR circuit using a PLL circuit, since the frequency of the strobe signal is adjusted, its phase information cannot be acquired correctly, and the amount of jitter possessed by the serial data cannot be estimated

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