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Mixed numerical system summator

An adder and mixed number technology, which is applied to calculations using number system representations, calculations using non-contact manufacturing equipment, etc., to achieve the effects of simple processing flow, low power consumption, and simple unit structure

Inactive Publication Date: 2010-05-19
BEIJING MXTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the design of special function arithmetic units has always been the core technology of foreign blockades, and there are few clear and detailed reports on the implementation methods and structures in the published literature.

Method used

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  • Mixed numerical system summator
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  • Mixed numerical system summator

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Experimental program
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Embodiment Construction

[0029] In order to understand the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0030] Such as figure 1 As shown, the mixed number system adder is mainly composed of a mixed adder unit, and realizes a mixed adder of n (n=4i, wherein i=1, 2, 3, 4, 5...) bits, It needs to be composed of n / 4 mixed adder units, and the carry method adopts the wave carry from low to high, that is, the output of the digital carry synthesizer of the low-order mixed adder unit is connected to the 4-bit addition of the adjacent high-order mixed adder unit The carry input terminal in the register. A mixed adder unit can realize the addition operation of a group of 4-bit binary numbers and the operation of decimal numbers represented by a group of 4-bit BCD codes. A hybrid adder unit consists of an input data strobe, an operand a data latch controller, an operand b data latch controller, a 4-bit adder, a ...

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Abstract

The mixed numerical system summator is mainly composed of a plurality of four-digit mixed summator units, wherein each mixed summator unit comprises an input data gate, an operand a data latch controller, an operand b data latch controller, a four-digit summator, a numerical system carry synthesizer, a numeric overflow judger, a numerical system normalizing device and a mixed numerical system four-digit operation result gate. The invention can realize stop-motion binary operation and triple-motion decimal number operation represented by a BCD code and can realize operation of different numerical systems with a hardware method, thus avoiding the numerical system conversion of software and improving the operation efficiency of the mixed numerical system. The calculation digit of the mixed numerical system summator can be flexibly expanded according to the calculation requirement. The summator has simple structure, small area, low power consumption and strong practicability and is convenient to realize on a chip.

Description

technical field [0001] The present invention relates to a mixed number system adder, in particular to a method for realizing a mixed number system adder and a specific hardware structure, which can be used in the design and manufacture of embedded processors, controllers and arithmetic units in special SOCs . Background technique [0002] Mixed number calculations are widely used. For example, in many electronic products such as prepaid electronic electricity meters, electronic water meters, electronic medical equipment CT, and electronic sphygmomanometers, there are problems with mixed number calculations and conversions. The operations are mainly binary operations. The traditional method is to complete it through software, which is inefficient and not conducive to the development and maintenance of embedded application systems. Today, with the rapid development of processors, controllers, and dedicated SoCs, driven by the market demand for embedded system application deve...

Claims

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Application Information

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IPC IPC(8): G06F7/50
Inventor 车德亮张奇荣
Owner BEIJING MXTRONICS CORP