Delay phase-locked loop with power-saving function

Abstract

The invention discloses a delay phase-locked loop with a power-saving function. The delay phase-locked loop comprises a voltage control delay loop, a voltage controller, a capacitor and a phase detector. The voltage control delay loop generates a delay periodic signal according to a reference periodic signal and the electric potential of the capacitor. The phase detector controls the voltage controller according to the phase difference of the reference periodic signal and the delay periodic signal. The voltage controller draws or outputs current to the capacitor so as to adjust the electric potential loaded by the capacitor according to a control signal of the phase detector. The voltage controller can close a current pump according to a close signal, and stops outputting or drawing current so as to save the electrical energy.

Description

technical field [0001] The invention relates to a delay-locked loop, in particular to a delay-locked loop with power-saving function. Background technique [0002] Please refer to figure 1 . figure 1 is a schematic diagram of a DRAM system 100 in the prior art. The DRAM system 100 includes a Delay Lock Loop (DLL) 110 and a Dynamic Random Access Memory (DRAM) 120 . The DRAM system 100 controls the DRAM 120 via the DLL 110 to access data. The delay-locked loop 110 is used to receive a reference period signal CLK, and delay the reference period signal CLK by a fixed phase to generate a delayed period signal CLK D . That is to say, the periodic signal CLK and CLK D The frequency is the same, but the periodic signal CLK D The phase of the fixed and periodic signal differs from the phase P D . DRAM 120 includes an input terminal I 1 , I 2 , whose input I 1 Used to receive the periodic signal CLK D , whose input I 2 Used to receive a close signal S CKE . When the DR...

AI Technical Summary

Problems solved by technology

Since the delay-locked loop 110 restarts after shutting down, it takes a long time to generate a fixed difference phase P- with the periodic signal CLK. D The periodic signal CLK D (that is, the periodic signal CLK D locked to the periodic signal CLK), and this relatively long time is too long for the DRAM 120 to be acceptable

Therefore, the DLL 110 cannot receive the shutdown signal S at the DRAM 120 CKE and closes with full close

In this way, the delay-locked loop 110 needs to continue to operate normally when the DLL 120 receives the shutdown signal CKE and shuts down, resulting in unnecessary power consumption and reducing the power consumption of the DRAM system 100 in the prior art. convenience

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