Bit line cutting high-performance buffer
A high-performance, buffer technology, applied in the fields of instruments, static memory, digital memory information, etc., can solve the problems of increasing the final chip area, increasing system power consumption, etc., and achieves the improvement of access speed, performance improvement, and charging and discharging speed. Effect
Inactive Publication Date: 2013-04-24
INST OF ACOUSTICS CHINESE ACAD OF SCI
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Not only increases the area of the final chip but also increases the power consumption of the system
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[0021] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0022] figure 1 A circuit diagram of a high-performance buffer is shown. The high performance buffer includes: a precharge circuit, a fast voltage detection circuit, an auxiliary discharge circuit and a control circuit.
[0023] The pre-charging circuit is composed of PMOS transistors P1 and P4, and under the control of the pre-charging signal provided by the register file, the bit line connected to the input and output of the buffer is simultaneously pre-charged. Taking the two-level division of the bit line as an example, that is, inserting one level of the high-performance buffer into the bit line, the load capacitance of the bit line is divided into two parts, so that the original load capacitance becomes half of the original. Thereby shortening the pre-charging time to half of the original.
[0024] While the pre-charging circuit is w...
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The invention provides a bit line cutting high-performance buffer, which is characterized in that the buffer comprises a pre-charging circuit, a rapid voltage detecting circuit, an auxiliary discharging circuit and a control circuit. When the pre-charging is started, the pre-charging circuit respectively charges a front and a post bit line simultaneously according to a pre-charging control signalprovided by a cut register while the control circuit cuts off the rapid voltage detecting circuit and the auxiliary discharging circuit so as to separate the front and post bit lines and prevent the preceding and post bit lines from affecting each other during pre-charging. When the pre-charging is ended, the control circuit switches on the rapid voltage detecting circuit so as to rapidly detect the change information of the preceding bit line level when the preceding bit line starts to discharge and then switches on the auxiliary discharging circuit so as to discharge the post bit line and greatly promote the charging and discharging speed of the bit lines.
Description
technical field [0001] The present invention relates to bit line division technology, in particular, the invention relates to a bit line division high-performance buffer. Background technique [0002] The drains of the transistors in the read part of the core cells used for storage in the register file are generally connected to the bit line. As the capacity of the register file increases, the load on the bit line is also increasing. At the same time, with the development of the CMOS process, in the 90nm, especially in the CMOS process below 90nm, the parasitic parameters due to interconnection have an impact on the performance of the circuit. more serious. Due to the influence of parasitic parameters, the pre-charging and discharging time of the bit line will become longer. [0003] In order to quickly read the information on the bit line, the traditional method adopts sensitive amplification or divides the memory into BANKs when the memory capacity is large, and forms a ...
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IPC IPC(8): G11C7/18
Inventor 王东辉闫浩张铁军侯朝焕
Owner INST OF ACOUSTICS CHINESE ACAD OF SCI