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Chip packaging structure and manufacture method thereof

A technology of a chip packaging structure and a manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of increased cost of the substrate 110, increased volume of the package structure 100, etc., and achieves a low-cost solution. Effect

Active Publication Date: 2010-06-16
CYNTEC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to make the substrate 110 have a sufficient carrying area, it is necessary to increase the size of the substrate 110, which will lead to an increase in the cost of the substrate 110 and an increase in the volume of the package structure 100.

Method used

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  • Chip packaging structure and manufacture method thereof
  • Chip packaging structure and manufacture method thereof
  • Chip packaging structure and manufacture method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0081] Figure 3A A cross-sectional view illustrating a chip package structure according to an embodiment of the present invention, Figure 3B draw Figure 3A Exploded view of the chip package structure. Please also refer to Figure 3A and Figure 3B The chip packaging structure 300 of this embodiment includes a substrate 310 , a plurality of chips 320 , a heat dissipation element E, a plurality of first conductive pillars 330 , an encapsulant 340 and a plurality of second conductive pillars 350 .

[0082] The substrate 310 has two opposite surfaces 312 , 314 . The substrate 310 is, for example, a direct copper bonding substrate, a printed circuit substrate, an aluminum-clad ceramic substrate, an insulated metal substrate, or a lead frame.

[0083] The chip 320 is disposed on the surface 312 of the substrate 310 and is electrically connected to the substrate 310 . The chip 320 can be electrically connected to the substrate 310 by wire bonding or flip chip bonding. In thi...

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PUM

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Abstract

The invention relates to a chip packaging structure which comprises a base plate, at least one chip, a heat radiating element, at least one first conducting post, a packaging colloid and at least one second conducting post, wherein the base plate is provided with a first surface and a second surface which are opposite to each other; the chip is configured on the first surface of the base plate; the heat radiating element is configured on the second surface of the base plate; each first conducting post has two opposite end surfaces, one end surface is configured on the first surface of the base plate and electrically connected with the base plate, and the other end surface extends to the direction far away from the base plate; a fixed groove is arranged between the two end surfaces and penetrates through the other end surface; the packaging colloid coats the base plate, the chips, part of heat radiating element and the first conducting posts and has two opposite surfaces, and one surface is exposed out of the surface of the heat radiating element, which is far away from the base plate; each second conducting post is arranged on the other surface of the packaging colloid and comprises a conductive pin part and a lug boss, and the lug boss of each second conducting post is fixed in a fixed groove of each first conducting post.

Description

technical field [0001] The present invention relates to a chip packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure with high voltage protection and a manufacturing method thereof. Background technique [0002] When designing a chip package structure that requires high voltage input (such as a power module that controls the power supply or an IGBT module that controls the motor drive), in order to comply with safety standards (such as: UL Standard) and ensure the normal operation of the package structure, It is usually necessary to consider the creepage distance and clearance distance between the voltage input end of the package structure (such as a lead) and the metal material (such as a heat sink) to avoid a gap between the lead and the heat sink. Conduction leads to an electrical short circuit, and prevents the instantaneous high voltage input from the lead pin from jumping directly to the low voltage end (that is, the he...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L23/48H01L23/34H01L21/56
CPCH01L2224/48137H01L2224/48091H01L2224/73265H01L21/565H01L2224/48227H01L2924/13055H01L2224/32225H01L24/73H01L2924/181H01L2924/00012H01L2924/00H01L2924/00014
Inventor 吕保儒温兆均陈大容吕俊弦
Owner CYNTEC