Chip packaging structure and manufacture method thereof
A technology of a chip packaging structure and a manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problems of increased cost of the substrate 110, increased volume of the package structure 100, etc., and achieves a low-cost solution. Effect
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[0081] Figure 3A A cross-sectional view illustrating a chip package structure according to an embodiment of the present invention, Figure 3B draw Figure 3A Exploded view of the chip package structure. Please also refer to Figure 3A and Figure 3B The chip packaging structure 300 of this embodiment includes a substrate 310 , a plurality of chips 320 , a heat dissipation element E, a plurality of first conductive pillars 330 , an encapsulant 340 and a plurality of second conductive pillars 350 .
[0082] The substrate 310 has two opposite surfaces 312 , 314 . The substrate 310 is, for example, a direct copper bonding substrate, a printed circuit substrate, an aluminum-clad ceramic substrate, an insulated metal substrate, or a lead frame.
[0083] The chip 320 is disposed on the surface 312 of the substrate 310 and is electrically connected to the substrate 310 . The chip 320 can be electrically connected to the substrate 310 by wire bonding or flip chip bonding. In thi...
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