Groove type power MOS device with improved terminal protective structure

Abstract

The invention relates to a groove type power MOS device, in particular to a groove type power MOS device with an improved terminal protective structure. A cellular area which is arranged on a semiconductor base plate and a terminal protective structure are arranged on the overlook surface of the MOS device, the cellular area comprises a plurality of cellulars which are connected in parallel and is arranged in the centre area of the semiconductor base plate; the terminal protective structure is arranged at the periphery of the cellular area, and the cellulars in the cellular area are connected to a whole body in parallel by an electro-conductive polycrystalline silicon which is arranged in the groove; the terminal protective structure comprises a partial pressure area which is arranged in the inner circle of the terminal protective structure and a cut off protective area which is arranged in the outer circle of the terminal protective structure; the partial pressure area adopts a groove structure, the groove structure comprises at least two partial pressure grooves, an ohmic contact hole is arranged between two adjacent partial pressure grooves, therefore, a second electro-conductive type layer which is arranged between two adjacent partial pressure grooves has equal electric potential with a source electrode, thereby improving the partial pressure capacity of the terminal protective area. An electric field is evenly divided by the partial pressure protective area, the size of the partial pressure protective area can be reduced, thereby reducing the area of a pipe core and reducing the cost, the groove type power MOS device with the improved terminal protective structure is compatible with the existing groove type power MOS technology and the manufacturing is convenient.

Description

technical field [0001] The invention relates to a trench power MOS device, in particular to a trench power MOS device with an improved terminal protection structure. Background technique [0002] Improving device performance and reducing cost are the two main sources of power to promote the continuous development of power MOS devices. The development of these two aspects mainly depends on the level of process processing and device design. As an important part of a power MOS device, the terminal protection structure not only directly affects the performance of the device, but also plays an important role in reducing the cost. In the prior art, the terminal protection structure, as described in Chinese patents ZL200710302461.4 and ZL 200810019085.2, is characterized in that the well runs through the entire terminal, and the trenches deep into the epitaxial layer separate the well regions into several mutually independent the well area. [0003] However, if figure 1 As shown...

AI Technical Summary

Problems solved by technology

This structure with extremely uneven distribution of electric field intensity may lead to premature breakdown of the MOS device in a local area when the forward bias voltage of the drain 14 is increased, deteriorating the breakdown performance of the device

[0005] 2. When a forward bias voltage is applied to the drain 14, the voltage of the MOS device is mainly composed of the cell trench 17 corresponding to the outermost cell area 1 and the voltage division protection area 2 corresponding to the cell area 1 When the P-well 7 between the voltage-dividing trenches 16 and the voltage-dividing protection region 2 correspond to the voltage-dividing trench 16 close to the cell region 1 for sharing, the remaining P-wells 7 on the voltage-dividing protection region 2 and the voltage divider groove 16 did not achieve the purpose of the voltage divider design, wasting the area of ​​the terminal protection area

For power MOS devices, the terminal protection structure occupies at least 20% of the die area, so the waste of area will lead to an increase in cost; if the total die area remains unchanged, the area of ​​the cell area must be sacrificed to make up, which will also increase Device on-resistance

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