Ultrathin semiconductor chip packaging structure and manufacturing process thereof

Abstract

The invention discloses an ultrathin semiconductor chip packaging structure, wherein double-layer leads are adopted for packaging a chip with a weld pad in double-row arrangement, and the two paths of leads do not mutually interfere, thereby further improving the reliability of electric connection; meanwhile, compared with the prior art, a single-side polymer is adopted for replacing the glass on the back surface of an original chip, a glass-silicon-polymer structure is adopted, the packaging thickness is further thinned, and the thickness can be reduced from the original 0.9mm to 0.5mm when in practical application, thereby greatly reducing the packaging volume of a semiconductor chip.

Description

technical field [0001] The invention relates to an ultra-thin semiconductor chip packaging structure and a manufacturing process thereof. Background technique [0002] The current wafer-level chip size packaging technology is to package and test the entire wafer, and then cut it to obtain a single chip. It adopts a glass-silicon-glass sandwich structure, and the packaged product size reaches 1: 1.3, is recognized by the industry as the world's leading semiconductor packaging technology. [0003] The chip packaging structure manufactured by the conventional wafer-level chip size packaging technology usually only uses a single-layer lead, and the number of pads of the packaged chip is limited due to the limited space on the soldering bump. The current idea is to use a double-layer lead package structure in order to save more space on the solder bump surface of the packaged chip for lead layout, thereby allowing more pads per unit area (for example, the pads are arranged in a ...

AI Technical Summary

Problems solved by technology

[0003] The chip packaging structure manufactured by conventional wafer-level chip size packaging technology usually only uses a single layer of leads. Due to the limited space on the soldering bump surface, the number of solder pads of the packaged chip is limited.

The current idea is to use a double-layer lead package structure in order to save more space on the solder bump surface of the packaged chip for lead layout, thereby allowing more pads per unit area (for example, the pads are arranged in a double row) However, the existing technical problem is that the use of double-layer leads will inevitably further increase the overall thickness and volume of the package structure; and the excessively thick package thickness is not conducive to the reduction of the width of the dicing lines between chips, thus It is impossible to manufacture more chips on the same size wafer, resulting in greatly reduced wafer utilization and increased packaging costs

In short, the existing wafer-level chip size packaging technology is still unable to implement effective packaging for multi-pad chips (such as chips with dual-row array of pads), which has great limitations.

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