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SATA (Serial Advanced Technology Attachment) linking layer transmitting data path and FIFO (First In First Out) storage optimizing method

A technology for data transmission and storage optimization, which is applied in the field of data transmission path and FIFO storage optimization in the link layer, and can solve the problems of long handshake response period between host and device primitives, inconsistency between state machine and control action, etc.

Active Publication Date: 2010-08-04
雷智数系统技术西安有限公司
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Problems solved by technology

[0005] The purpose of the present invention is to provide a SATA link layer transmission data path and FIFO storage optimization method, which solves the inconsistency of the state machine and control action in the background technology and the relatively long response period of the host and device primitive handshake. question

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  • SATA (Serial Advanced Technology Attachment) linking layer transmitting data path and FIFO (First In First Out) storage optimizing method
  • SATA (Serial Advanced Technology Attachment) linking layer transmitting data path and FIFO (First In First Out) storage optimizing method

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Embodiment Construction

[0047] like figure 1 As shown, the present invention designs a SATA link layer sending data path based on FPGA logic. It introduces a multiplexer (mux), primitive / invalid data transmission control and ROM module, and adopts a series of control and optimization of FIFO storage strategy, so that the link layer can ensure the consistency of the physical layer FIFO output data. The data transmission and each driving action can be discontinuous, which reduces the timeliness requirements for state transfer and improves design flexibility.

[0048] At the same time, use the physical layer fifo (Phy FIFO) to program the empty and full flags. In the valid data sending state, as long as the programming is not full, and there is data or CRC from the Trans FIFO, it will be written into the Phy FIFO; in the primitive sending state, the PHY FIFO is empty , the programming is empty and valid, and then write in it. In this way, the Phy FIFO can make full use of its capacity when sending dat...

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Abstract

The invention relates to an SATA (Serial Advanced Technology Attachment) linking layer transmitting data path and an FIFO (First In First Out) storage optimizing method. The data path comprises a transmission layer FIFO and CRC (Cyclical Redundancy Check) transmitting module and input ends of a first multiplexer and a first scrambler in sequential connection, a primitive / invalid data transmitting module, a ROM (Read-Only Memory) and input ends of a second scrambler and a second multiplexer in sequential connection, wherein the first scrambler and the second multiplexer are connected with a third multiplexer; and the third multiplexer is sequentially connected with a 8B / 10B coder and a transmitting physical layer FIFO. The physical layer FIFO is used for programming empty and full marks and can thoroughly use the capacity of data during data transmission; when different primitive switches are transmitted, the physical layer FIFO continuously maintains about 10 D words; a delay period caused by data delay in the physical layer FIFO is largely shortened, thereby quickening a response period of the primitive handshake of a host and equipment.

Description

technical field [0001] The invention relates to a link layer transmission data path and a method for optimizing FIFO storage, in particular to a SATA link layer transmission data path and a method for FIFO storage optimization Background technique [0002] Serial ATA (SATA) is a new generation of storage technology to replace ATA, with a transmission speed of 150MB / s (SATA1.0) or 300MB / s (SATA2.0), and is widely used. Analyzing the SATA protocol standard, the SATA controller can be divided into 4 layers: application layer, transport layer, link layer and physical layer. [0003] When the Sata transport layer has a frame transmission request (the request frame transmission signal is valid), the link layer needs to perform a series of actions, and finally write the frame and primitive sequence to be sent into the physical layer FIFO. These include driving the PrimitXmtCtl module to send corresponding control primitives, driving the FIFO read enable signal to read the effectiv...

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Application Information

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IPC IPC(8): H04L29/08
Inventor 刘升史宝祥
Owner 雷智数系统技术西安有限公司
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