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LDPC decoder with low power consumption

A decoder and check code technology, which is applied in the field of low-density parity check code decoders, can solve the problems of complex LDPC decoding structure, large power consumption, and large hardware consumption, and achieve low power consumption and low power consumption. Effect of reduction and reduction of power consumption

Active Publication Date: 2013-01-30
SOI MICRO CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the H matrix is ​​usually huge and sparse, the structure of LDPC decoding is usually complex and consumes a lot of hardware
Because of the high power consumption of decoding, this is a fatal weakness for many wireless mobile terminal equipment

Method used

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  • LDPC decoder with low power consumption
  • LDPC decoder with low power consumption
  • LDPC decoder with low power consumption

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Embodiment Construction

[0034] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0035] figure 1 It is a structural schematic diagram of a low-power LDPC decoder provided by the present invention. The decoder is composed of an input buffer, a check node operation unit, a variable node operation unit, a storage unit, an output buffer, a control logic unit and an interconnection network. Among them, the decoder adopts a partially parallel decoding structure, and uses x variable node operation units, y check node operation units, 1 output buffer and 1 output buffer, and x and y are the basic matrix of H respectively. The number of columns and rows.

[0036] The operation unit of the check node is composed of an operation unit that calculates the minimum input value and the second minimum value of the in...

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Abstract

The invention discloses a parity check code decoder with low power consumption and low density. The decoder consists of an input buffer, check node operation units, variable node operation units, a storage unit, output buffers, a control logic unit and the Internet, wherein the decoder adopts a partial parallel decoding structure and totally uses x variable node operation units, y check node operation units, one output buffer and one output buffer, where x and y are respectively the column number and the row number of the basis matrix of H. Compared with the conventional LDPC decoder, the invention does not introduce any hardware consumption when reducing the power consumption of iteration coding, and has no influence on the error code output performance of the decoder.

Description

technical field [0001] The invention relates to the technical fields of high-speed wireless digital communication and optical fiber communication, in particular to a low-power-consumption low-density parity-check code (LDPC) decoder. Background technique [0002] In the process of data transmission and storage, various noises are always introduced, such as random noise, synchronization loss during demodulation, and multipath effects in wireless transmission. Due to the existence of these noises, the data transmission rate and transmission quality under a certain bandwidth are greatly limited. [0003] With the continuous progress of modern communication technology, the communication system is gradually developing towards higher throughput, larger capacity and higher reliability, and error control coding has been widely used. Low-density parity-check code (LDPC) is a very important class of codes in error control codes. It was proposed by Robert Gallager in [R.G.Gallager, Lo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
Inventor 郭琨黑勇周玉梅
Owner SOI MICRO CO LTD