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VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter

A technology of motion compensation and structural design, applied in the field of video decoding, can solve the problems of large amount of calculation, high time occupied by motion compensation, time-consuming data reading, etc., to reduce access, reduce data bandwidth, and improve efficiency and speed. Effect

Inactive Publication Date: 2010-11-17
XI AN JIAOTONG UNIV
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Problems solved by technology

During the entire decoding process of H.264, motion compensation takes a lot of time, and this module is characterized by time-consuming data reading and a large amount of calculation

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  • VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter
  • VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter
  • VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter

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Embodiment Construction

[0020] figure 1 Shown is the overall architecture design of the motion compensation module. As can be seen in the figure, this module can be roughly divided into three parts. The following are introduced separately.

[0021] The first part is the module input and output interface. Among them, the input interface is an off-chip memory, from which information such as reference frame pixel data, motion vector and block division type is read. The output interface is to write the reconstructed current frame data into the external memory, which contains the values ​​of two components of brightness and chrominance.

[0022] The second part is the hierarchical on-chip memory, which is used to store the required data read from the external memory. In order to reduce the read bandwidth and improve the data multiplexing rate, at the same time, in order to realize the self-adaptive variable size block processing, this paper adopts a three-layer on-chip buffer structure, including the ...

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Abstract

The invention discloses a VLSI (Very Large Scale Integration) structure design method for a parallel flowing motion compensating filter. By carrying out parallel calculation on a brightness pixel point and a chroma pixel point of a motion compensation module and adopting an inner pipelining processing way of a self-adaption block, the processing time on the whole decoding is reduced, and the system throughput is improved. By adopting layering framework design on an on-chip memory and further optimizing an access way, the access on an off-chip memory is reduced. By adopting a data multiplexingtechnology of a reference pixel and adopting a macro-subblock updating treatment technology, time on reading data is obviously saved, and data reading bandwidth is reduced, thereby improving the decoding efficiency of a decoder and decoding performance.

Description

technical field [0001] The invention belongs to the field of video decoding, in particular to a VLSI structure design method of a parallel pipeline motion compensation filter. Background technique [0002] The H.264 video codec standard is currently the mainstream codec standard in the world. As a new generation of video coding standard, H.264 video coding standard has basically the same coding framework as previous video coding standards, but the coding efficiency has been greatly improved. The price is that the calculation process is more complicated and the calculation amount is larger, which increases the difficulty of hardware implementation of the video decoder. Therefore, when designing a video decoding chip, efforts should be made to improve decoding efficiency and reduce area and power consumption. However, in the field of video decoding, the power consumption and on-chip area of ​​the device are always subject to various constraints. It is necessary to implement...

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Application Information

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IPC IPC(8): H04N7/26H04N9/78H04N19/513
Inventor 兰旭光惠苗郜金金李兴玉郑南宁
Owner XI AN JIAOTONG UNIV
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