VLSI (Very Large Scale Integration) structure design method for parallel flowing motion compensating filter

Abstract

The invention discloses a VLSI (Very Large Scale Integration) structure design method for a parallel flowing motion compensating filter. By carrying out parallel calculation on a brightness pixel point and a chroma pixel point of a motion compensation module and adopting an inner pipelining processing way of a self-adaption block, the processing time on the whole decoding is reduced, and the system throughput is improved. By adopting layering framework design on an on-chip memory and further optimizing an access way, the access on an off-chip memory is reduced. By adopting a data multiplexingtechnology of a reference pixel and adopting a macro-subblock updating treatment technology, time on reading data is obviously saved, and data reading bandwidth is reduced, thereby improving the decoding efficiency of a decoder and decoding performance.

Description

technical field

[0001] The invention belongs to the field of video decoding, in particular to a VLSI structure design method of a parallel pipeline motion compensation filter. Background technique

[0002] The H.264 video codec standard is currently the mainstream codec standard in the world. As a new generation of video coding standard, H.264 video coding standard has basically the same coding framework as previous video coding standards, but the coding efficiency has been greatly improved. The price is that the calculation process is more complicated and the calculation amount is larger, which increases the difficulty of hardware implementation of the video decoder. Therefore, when designing a video decoding chip, efforts should be made to improve decoding efficiency and reduce area and power consumption. However, in the field of video decoding, the power consumption and on-chip area of ​​the device are always subject to various constraints. It is necessary to implement...

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