40results about How to "Reduce data bandwidth" patented technology

A remote measuring system includes a test apparatus connected to a sensor for testing an object, a communication unit, and a remoteoperating unit. Control signals may be sent from this operating unit to the communication unit to operate the test apparatus. A data processing unit performs a compression process of a first flow of test data emanating from the test apparatus and sends a second flow of test data to the operating unit. The data processing unit performs a quantisation process, which may be controlled through control signals at the operating unit. A remotely located expert may thus receive a direct and qualified impression of the procedure and the inspection results and give advice on correct procedures or on changing the manner of the recording. By obtaining support from experts, time is saved and the transfer of know-how and the use of experts is improved.

The invention discloses a VLSI (Very Large Scale Integration) structure design method for a parallel flowing motion compensating filter. By carrying out parallel calculation on a brightness pixel point and a chroma pixel point of a motion compensation module and adopting an inner pipelining processing way of a self-adaption block, the processing time on the whole decoding is reduced, and the system throughput is improved. By adopting layering framework design on an on-chip memory and further optimizing an access way, the access on an off-chip memory is reduced. By adopting a data multiplexingtechnology of a reference pixel and adopting a macro-subblock updating treatment technology, time on reading data is obviously saved, and data reading bandwidth is reduced, thereby improving the decoding efficiency of a decoder and decoding performance.

The invention discloses a large-scale image data processing system and method. The system comprises the components of: a high-speed visual chip core processing module used for carrying out hierarchical multi-stage parallel deep learning algorithm processing on input image data and comprising a processing core module and a processing block array, the processing block array comprises M * N processing blocks which are connected and configurable, M and N are positive integers, and each processing block comprises a micro-processing unit array; wherein the processing core module is used for connection configuration, operation control and state monitoring of the whole processing block array, and can realize global image data processing; wherein each processing block in the processing block arrayis used for parallel processing of various images with different resolutions; wherein the micro-processing unit array comprises P micro-processing units, and P is a positive integer and is used for realizing parallel processing of pixel-level data. The system has the comprehensive performances of simple structure, low power consumption, high energy efficiency, high data throughput rate and high target identification precision.

The present invention provides a processing method and system for image data in a DRAM. The method comprises the following steps: sending, by a GBUS, a request command of reading and writing image data; receiving, by a GDAM, the request command from the GBUS, converting the request command to a request signal corresponding to a DRAM controller, and sending the request signal to a DBUS; receiving, by the DBUS, the request command from the GDAM, and processing the image data in the DRAM by using the DRAM controller. According to the method, the reading and writing of the image data in the DRAM are finished, convenience for accessing the image data in the DRAM is improved, and the highest efficiency of the DRAM is achieved; the effective measures are taken to ensure that storage space of the DRAM is used as little as possible, data bandwidth of the DRAM as little as possible is consumed, and the access efficiency of the DRAM as high as possible is achieved.

The invention discloses a method and device for dynamically allocating a physical address and an electronic device. The method comprises the following steps: detecting whether an event of dynamicallyallocating a physical address of data accessed by an application program occurs; According to the detection results of events, the time order of accessing data in the process of application program running is obtained; Obtaining a logical address of the data stored in advance in the application program according to the detection result of the event; According to the time order and logical addressof the data, the physical address is assigned to the data so that the physical address of the data corresponds to the time order. As such, that proportion of time the system spend accessing the storage as a contiguous physical address increase during the running of the application, thereby increasing the efficiency of the system storage access to the storage.

The invention puts forward a neural network processor based on efficient multiplex data stream, and a design method, and relates to the technical field of the hardware acceleration of neural network model calculation. The processor compares at least one storage unit, at least one calculation unit and a control unit, wherein the at least one storage unit is used for storing an operation instruction and arithmetic data; the at least one calculation unit is used for executing neural network calculation; and the control unit is connected with the at least one storage unit and the at least one calculation unit for obtaining the operation instruction stored by the at least one storage unit via the at least one storage unit, and analyzing the operation instruction to control the at least one calculation unit, wherein the arithmetic data adopts a form of the efficient multiplex data stream. By use of the processor, the efficient multiplex data stream is adopted in a neural network processing process, a weight and data only need to be loaded into one row of calculation unit in a calculation unit array each time, the bandwidth of data on chip is lowered, a data sharing rate is improved, and energy efficiency is improved.

This invention relates to ARQ mechanism for data link layer error control in the wireless data communication system, and reforms the unreliable wireless physical link into the reliable data logical link to provide the reliable data transmission sphere for the network layer. Compared with the existing ARQ mechanism, this invention greatly increases the acknowledgement rate, yet does not reduce the throughput rate, greatly lowers the data band-width of acknowledgement, and therefore more data band-width can send the backward data to support two-way data transmission. By fixing the length bit map and relative bias, in accordance with error data PDU distribution, this invention automatically select the acknowledgement type with the highest acknowledgement efficiency to confirm the part of data PDU that need the most acknowlegement in the reception window.

The invention provides an image processing method, device and system. The image processing method comprises the steps that received images are converted into an ultra high-definition image; a reference image is determined on the basis of the ultra high-definition image obtained after conversion and sent to a display unit to be displayed; the current-frame ultra high-definition image is compared with the reference image to determine an image area, generating changes compared with the reference image, in the current-frame ultra high-definition image; and image data corresponding to the image area is sent to the display unit to allow the display unit to update the currently-displayed reference image according to the image data. According to the method, the transmitted data amount is decreased, the requirement on the data bandwidth is lowered, and the refreshing rate is increased.