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High-speed asynchronous data acquisition system

An asynchronous data and acquisition system technology, applied in the field of data communication, can solve the problem that PLL accuracy cannot be guaranteed, achieve the effect of improving reliability and adaptability, and increasing data acquisition speed

Inactive Publication Date: 2010-12-22
杭州中科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional sampling systems usually use a synchronization mechanism. However, inside the FPGA, in order to achieve better synchronization, the internally generated PLL first multiplies and then divides the frequency. For applications with relatively low sampling frequencies, the PLL accuracy cannot be guaranteed

Method used

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Examples

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no. 1 example

[0045] The configuration of the high-speed asynchronous data acquisition system based on AHB bus of the present invention is: the embedded processor core is the SUMSUNG S3C2410A of ARM920T; The model is EP2C70672C8 of Altera's Cyclone II series; the high-speed asynchronous data transmission instructions based on the AHB bus are issued by the ARM9 processor as the master module, and processed and responded by the data acquisition module as the slave module. The basic main structure of the AHB bus also includes multiplexers from the master module to the slave module and from the module to the master module, as well as decoders, arbitrators, virtual slave modules, and virtual master modules.

[0046] figure 2 It is a block diagram of the data acquisition and DA conversion module of the present invention. The data acquisition and DA conversion module is composed of a selector 21 , an AD converter 22 , a buffer selector 23 , buffers 24 and 25 , and a selector 26 . The selector 2...

no. 2 example

[0067] The high-speed data acquisition system of the present invention is applied to the GPS receiving system, and the intermediate frequency signal frequency of its collection is 16.368MHz, and the sampling frequency is 16.368MHz or 26MHz, and the AHB bus clock uses the clock of ARM9 internal PLL frequency multiplication, up to 200MHz. When the collected data width is 2bit, the sampling frequency can be up to 100M.

no. 3 example

[0069] In the high-speed data acquisition system of the present invention, a self-test mode is added. When the use environment changes, the self-test mode can be used to judge whether the system is working normally. Once an abnormality occurs, the configuration can be manually adjusted to adapt to the environment. If necessary, keep the working mode of the system normal.

[0070] The self-test signal in the self-test mode is generated locally, and the self-test signal is sent to the data acquisition module, and the output fixed data is stored in SDRAM. Therefore, it is only necessary to check the data in SDRAM to detect whether the system is working normally.

[0071] In the data acquisition system of the present invention, the model selected by the FPGA chip is the EP2C70672C8 of the Cyclone II series of Altera Company; the S3C2410A of Samsung Corporation is selected by the ARM9, and the ARM920T is used as the core; the HY57V5616 of Hyundai is selected by the SDRAM chip.

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Abstract

The invention belongs to the technical field of data communication, and relates to a high-speed asynchronous data acquisition system based on an AHB bus. The high-speed asynchronous data acquisition system comprises a field programmable gate array (FPGA), an embedded processor core ARM9, an off-chip SDRAM, a JTAG interface and an off-chip personal computer (PC), wherein the embedded processor core ARM9 is used for starting data acquisition, data reading and data storage; the off-chip SDRAM is used for data storage; the JTAG interface is used for transmitting the data from the SDRAM to the PC for storage so as to facilitate follow-up treatment; the FPGA comprises a data acquisition module, an AHB bus module and a wrap module; and the data acquisition module is used for realizing data acquisition and converting the data into an appropriate format so as to be read by the bus, the AHB bus module is used for connecting an AHB master and an AHB slave, and the wrap module is used for converting ARM9CPU time sequence into AHB master time sequence and realizing address conversion by mapping the address of the ARM9CPU. Asynchronous working mechanism and synchronization treatment are adopted for data acquisition and transmission, the asynchronous working mechanism improves the data acquisition speed, and the synchronization treatment ensures the reliability of the sampling circuit, can inspect the system function under different environments and obviously improves the reliability and adaptability of the acquisition system; and the invention can be widely applied to the fields of data communication, integrated circuit design verification and the like.

Description

technical field [0001] The invention belongs to the technical field of data communication and relates to a data acquisition system, in particular to a high-speed data acquisition system based on an AHB bus. Background technique [0002] A / D sampling of various data is involved in the field of data communication technology. With the rapid development of modern communication technology, high-speed and wide-range sampling frequency requirements are required for A / D sampling of data, and many A / D sampling systems have emerged. [0003] The input and output data transmission methods of the high-speed data acquisition system in the prior art include program transmission, interrupt transmission and DMA transmission. The reliability of conditional program transfer is poor, and the reliability of conditional program transfer that passes the device status test can be improved, but at the cost of lower host efficiency. Interrupt transfer means that the device sends an interrupt reque...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/05G06F13/38G06F13/40
Inventor 冯华星何文涛李晓江
Owner 杭州中科微电子有限公司
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