Chip packaging structure and manufacturing method thereof
A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., and can solve problems such as high cost
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no. 1 example
[0055] Please refer to Figure 2M , which is a schematic diagram of a chip packaging structure according to the first embodiment of the present invention. The chip package structure 200 includes: a chip module, several circuit structures 214 , a filling material layer 240 , and a rewiring layer 260 . The chip module includes a chip 220 having an active surface 220a. Several circuit structures 214 are disposed around the chip 220 . Please also refer to Figure 2B , each circuit structure 214 has a circuit 216 and a first surface 214a. exist Figure 2M Among them, the filling material layer 240 covers the chip 220 and the circuit structures 214 . The filling material layer 240 has a second surface 240a, and the active surface 220a, each first surface 214a and the second surface 240a are substantially coplanar. The material of the filling material layer 240 can be a photo-imageable material or a non-photosensitive material, and is preferably a molding compound, but not limi...
no. 2 example
[0066] Compared with the first embodiment, this embodiment omits the above Figure 2L In the steps of forming a plurality of second openings 2661 in the second dielectric layer 262 and accommodating the conductive material 2662 in the plurality of second openings 2661, the above-mentioned steps are omitted. Figure 2M The step of setting several external connectors 272 on the conductive material 2662 to form a Figure 4 The package of the chip package structure 400 . That is to say, the manufacturing method of the chip packaging structure 400 of this embodiment includes the steps in Figures 2A to 2K and Figure 2M part of the steps. Figure 4 The rewiring layer 460 of the chip package structure 400 does not have openings, so no external connectors are provided on this side of the chip package structure 400, and only the external connector 474 on the other side is used as a pipe for external connection.
no. 3 example
[0068] Compared with the first embodiment, this embodiment omits the aforementioned Figure 2E The step of accommodating the conductive material 2402 in the through hole 2401 of the filling material layer 240 is replaced by the following steps: Please refer to Figure 5 A conductive layer 592 is disposed on the other second surface 540 b of the filling material layer 540 , the sidewall of the through hole 5401 of the filling material layer 540 , and the part of the circuit 516 exposed from the through hole 5401 . Furthermore, a dielectric layer 594 is disposed on the conductive layer 592 , and the dielectric layer 594 and the filling material layer 540 can be made of the same material or different materials. Moreover, the dielectric layer 594 has several openings 5921 exposing the conductive layer 592 . The forming method of these openings 5921 is preferably exposing and developing, but not limited thereto. Other methods such as laser drilling, mechanical drilling or punching...
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