CMOSFETs structure for controlling threshold voltage of device and manufacturing method thereof

Abstract

The invention discloses a CMOSFETs structure for controlling the threshold voltage of a device by using a gate stack structure and a manufacturing method thereof. The structure comprises a silicon substrate, a SiO2 boundary layer growing on the silicon substrate, a high k gate dielectric layer deposited on the SiO2 boundary layer, an ultra thin metal layer deposited on the high k gate dielectric layer, a high k gate dielectric layer deposited on the ultra thin metal layer structure and a metal gate layer deposited on the high k gate dielectric stack structure. The manufacturing method comprises the following steps: respectively depositing the ultra thin metal layers in the high k gate dielectric layers in the regions of NMOS and PMOS devices, and regulating the flat band voltage of the devices by using positive or negative charges formed by the ultra thin metal layers in the high k gate dielectric layers, thereby controlling the threshold voltage of the devices. The invention not only can enhance the interface dipole between the high k gate dielectric layer and the SiO2 boundary layer in the CMOS device, but also can well control the type and the number of permanent charges in the high k gate dielectric layer, thereby effectively controlling the threshold voltage of the device.

Description

technical field [0001] The invention relates to the technical field of high-k gate dielectric and metal gate structure in nanotechnology CMOS technology, in particular to a CMOSFETs structure and a manufacturing method thereof which utilize a gate stack structure to control device threshold voltage. Background technique [0002] The application of key core technologies of 22nm and below process integrated circuits is an inevitable trend in the development of integrated circuits, and it is also one of the topics that major international semiconductor companies and research organizations are competing to research and develop. CMOS device gate engineering research centered on "high-k gate dielectric / metal gate" technology is the most representative key core process in 22nm and below technologies, and related material, process and structure research has been extensively carried out middle. [0003] For a CMOS device with a high-k gate dielectric / metal gate structure, its leakag...

AI Technical Summary

Problems solved by technology

On the other hand, due to the Fermi level pinning effect, V fb Due to the existence of problems such as roll-off effect, the adjustment of the threshold voltage of NMOS devices and PMOS devices using the above methods can only be limited within a certain range.

Images