Structure of transverse diffusion metal oxide semiconductor field effect transistor

Abstract

The invention discloses a structure of a transverse diffusion metal oxide semiconductor field effect transistor, comprising a P-type substrate, an N+ type buried layer, an N-type epitaxial layer, a P-type well, an N-type well, a drain electrode region, a source electrode region and a body region, wherein the N+ type buried layer is located between the P-type substrate and the N-type epitaxial layer, the P-type well is in contact with the N+ type buried layer, the source electrode region and the body region are located in the P-type well, the N-type well is located in the N-type epitaxial layer, and the drain electrode region is located in the N-type well. When a high voltage is applied to a drain electrode and the P-type substrate is grounded, a breakdown voltage of the P-type substrate is improved because the N+ type buried layer is separated from the P-type substrate and the N-type epitaxial layer, therefore, the occurrence of PN-junction breakdown can be avoided.

Description

technical field [0001] The invention relates to a lateral diffusion metal oxide semiconductor field effect transistor structure, in particular to a metal oxide semiconductor field effect transistor structure in which a P-type substrate and an N type epitaxial layer are separated by an N+ type buried layer. Background technique [0002] With the development of the semiconductor industry, high-power components are often used in many power electronics. Among them, the lateral diffused metal oxide semiconductor field effect transistor (Lateral Diffused MOSFET, LDMOS) is easier to integrate with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor) Semiconductor, CMOS) process compatible and widely used. [0003] refer to figure 1 , a schematic diagram of a prior art LDMOS. Such as figure 1 As shown, the prior art LDMOS1 includes a P-type substrate (substrate) 10, a P+ type buried layer (B / L, buried layer) 12, an N type epitaxial layer (EPI, epitaxi...

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Problems solved by technology

[0009] When the LDMOS 1 is turned off, the drain terminal D is connected to a high voltage (600V), and the source terminal S and the body terminal B are grounded to close the LDMOS 1. At this time, the connection line (not shown) connected to the drain terminal D has a high voltage of 600V. voltage, which will cause a breakdown between the drain region and the source region of LDMOS 1, and cause LDMOS1 to fail, or even cause permanent damage

Although the thick oxide layer isolation region 92 can improve the protection effect, the protection effect is still very limited, so an LDMOS structure that can ensure that the PN junction collapse does not occur is required

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