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Photoetching method

A photolithography and photoresist technology, applied in the field of photolithography, can solve the problems of increased line width and roughness, and achieve the effects of reducing line width roughness, accurate position, and improving quality

Active Publication Date: 2012-08-22
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention solves the problem of increasing the line width and roughness by trimming the photoresist pattern after developing in the prior art

Method used

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Embodiment approach

[0011] Based on this, in one embodiment of the photolithography method of the present invention, when dry etching is used to trim the developed photoresist pattern, a bias voltage is used.

[0012] In the above embodiments, the bias voltage is used to control the reaction position of the etching gas and the photoresist pattern, so that the etching reaction occurs between the etching gas and the rough part of the photoresist pattern, thereby reducing the line width roughness of the photoresist pattern.

[0013] In current photolithography methods, in order to reduce light reflection, a bottom anti-reflective coating (BARC, Bottom Anti Reflective Coating) is usually formed on the etched layer first, and then photoresist is coated on the bottom anti-reflective layer. However, the existing etching process of the bottom anti-reflection layer also uses a bias voltage. In view of this, the bias voltage method is adopted in combination with the trimming of the photoresist pattern menti...

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Abstract

The invention discloses a photoetching method comprising the following steps of: after developing, pruning a photoresist pattern by using a dry-method etching method; and adopting the bias voltage during dry-method etching. The photoetching method ensures that the positions for etching gas ions and carrying out an etching reaction on the photoresist pattern are more accurate and improves the quality for pruning the photoresist pattern, thereby correspondingly reducing the line-width roughness of a semiconductor formed by subsequent etching by pruning the photoresist pattern.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a photolithography method. Background technique [0002] Defects in the semiconductor manufacturing process are a major factor affecting the yield and performance of semiconductor devices. Especially for today's semiconductor manufacturing industry, when the device size is reduced below 100nm, the requirements for photolithography and etching processes are particularly stringent. For example, in the photolithography process, the line edge roughness (LER, Line Edge Roughness) and the line width roughness (LWR, Line Width Roughness) are important indicators that the process pays more attention to. Existing experimental studies have shown that when the line edge roughness and line width roughness are high, the device performance will deteriorate accordingly. For example, for SRAM, if the line width roughness of the photoresist pattern in the gate formation process is hig...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/36
Inventor 张海洋黄怡张世谋
Owner SEMICON MFG INT (SHANGHAI) CORP